Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752449AbdHIUKY (ORCPT ); Wed, 9 Aug 2017 16:10:24 -0400 Received: from mail-it0-f53.google.com ([209.85.214.53]:37252 "EHLO mail-it0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752061AbdHIUI6 (ORCPT ); Wed, 9 Aug 2017 16:08:58 -0400 From: Tycho Andersen To: linux-kernel@vger.kernel.org Cc: linux-mm@kvack.org, kernel-hardening@lists.openwall.com, Marco Benatto , Juerg Haefliger , Juerg Haefliger Subject: [PATCH v5 04/10] arm64: Add __flush_tlb_one() Date: Wed, 9 Aug 2017 14:07:49 -0600 Message-Id: <20170809200755.11234-5-tycho@docker.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170809200755.11234-1-tycho@docker.com> References: <20170809200755.11234-1-tycho@docker.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 873 Lines: 31 From: Juerg Haefliger Add a hook for flushing a single TLB entry on arm64. Signed-off-by: Juerg Haefliger Tested-by: Tycho Andersen --- arch/arm64/include/asm/tlbflush.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index af1c76981911..8e0c49105d3e 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -184,6 +184,14 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end isb(); } +static inline void __flush_tlb_one(unsigned long addr) +{ + dsb(ishst); + __tlbi(vaae1is, addr >> 12); + dsb(ish); + isb(); +} + /* * Used to invalidate the TLB (walk caches) corresponding to intermediate page * table levels (pgd/pud/pmd). -- 2.11.0