Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752305AbdHJHXn (ORCPT ); Thu, 10 Aug 2017 03:23:43 -0400 Received: from mx.socionext.com ([202.248.49.38]:26858 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751455AbdHJHXm (ORCPT ); Thu, 10 Aug 2017 03:23:42 -0400 From: Katsuhiro Suzuki To: Michael Turquette , Stephen Boyd , Masahiro Yamada , linux-clk@vger.kernel.org Cc: Masami Hiramatsu , Jassi Brar , linux-kernel@vger.kernel.org, Katsuhiro Suzuki Subject: [PATCH 1/2] clk: uniphier: add audio system clock Date: Thu, 10 Aug 2017 16:23:45 +0900 Message-Id: <20170810072346.32299-1-suzuki.katsuhiro@socionext.com> X-Mailer: git-send-email 2.13.2 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1981 Lines: 47 Add clock for audio subsystem (AIO) and SoC internal audio codec (EVEA) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki --- drivers/clk/uniphier/clk-uniphier-sys.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index ad0218182a9f..7c4528d0fb6e 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -57,6 +57,14 @@ #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \ UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch)) +#define UNIPHIER_LD11_SYS_CLK_AIO(idx) \ + UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \ + UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0) + +#define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \ + UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \ + UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1) + const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ @@ -158,6 +166,8 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { /* Index 5 reserved for eMMC PHY */ UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */ UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), + UNIPHIER_LD11_SYS_CLK_AIO(40), + UNIPHIER_LD11_SYS_CLK_EVEA(41), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), @@ -194,6 +204,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14), UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12), UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13), + UNIPHIER_LD11_SYS_CLK_AIO(40), + UNIPHIER_LD11_SYS_CLK_EVEA(41), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), -- 2.13.2