Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752352AbdHJHXs (ORCPT ); Thu, 10 Aug 2017 03:23:48 -0400 Received: from mx.socionext.com ([202.248.49.38]:26860 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751440AbdHJHXp (ORCPT ); Thu, 10 Aug 2017 03:23:45 -0400 From: Katsuhiro Suzuki To: Michael Turquette , Stephen Boyd , Masahiro Yamada , linux-clk@vger.kernel.org Cc: Masami Hiramatsu , Jassi Brar , linux-kernel@vger.kernel.org, Katsuhiro Suzuki Subject: [PATCH 2/2] clk: uniphier: add video input subsystem clock Date: Thu, 10 Aug 2017 16:23:46 +0900 Message-Id: <20170810072346.32299-2-suzuki.katsuhiro@socionext.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170810072346.32299-1-suzuki.katsuhiro@socionext.com> References: <20170810072346.32299-1-suzuki.katsuhiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1656 Lines: 41 Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki --- drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 7c4528d0fb6e..c60aa586fea7 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -65,6 +65,10 @@ UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \ UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1) +#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \ + UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \ + UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2) + const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */ UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */ @@ -168,6 +172,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), UNIPHIER_LD11_SYS_CLK_AIO(40), UNIPHIER_LD11_SYS_CLK_EVEA(41), + UNIPHIER_LD11_SYS_CLK_EXIV(42), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8), @@ -206,6 +211,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13), UNIPHIER_LD11_SYS_CLK_AIO(40), UNIPHIER_LD11_SYS_CLK_EVEA(41), + UNIPHIER_LD11_SYS_CLK_EXIV(42), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), -- 2.13.2