Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752330AbdHJH5o (ORCPT ); Thu, 10 Aug 2017 03:57:44 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:36384 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751511AbdHJH5n (ORCPT ); Thu, 10 Aug 2017 03:57:43 -0400 Subject: Re: [PATCH] mips: Fix using smp_processor_id() when preemptible To: , , , CC: Corey Minyard References: <1502313950-725-1-git-send-email-minyard@acm.org> From: Marcin Nowakowski Message-ID: Date: Thu, 10 Aug 2017 09:57:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1502313950-725-1-git-send-email-minyard@acm.org> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.2.5] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1526 Lines: 51 Hi Corey, This has already been fixed here: https://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=21da5332327b6d183bd93336ecf29c70bc609b7b https://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=735302665c353d6756e7fa2a2cf41b039299f732 Marcin On 09.08.2017 23:25, minyard@acm.org wrote: > From: Corey Minyard > > I was getting the following: > > BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 > caller is pcibios_set_cache_line_size+0x10/0x58 > > pcibios_set_cache_line_size() used current_cpu_data outside of > an unpreemptible context. > > Signed-off-by: Corey Minyard > --- > arch/mips/pci/pci.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c > index bd67ac7..afd2f8a 100644 > --- a/arch/mips/pci/pci.c > +++ b/arch/mips/pci/pci.c > @@ -28,9 +28,11 @@ EXPORT_SYMBOL(PCIBIOS_MIN_MEM); > > static int __init pcibios_set_cache_line_size(void) > { > - struct cpuinfo_mips *c = ¤t_cpu_data; > + struct cpuinfo_mips *c; > unsigned int lsize; > > + preempt_disable(); > + c = ¤t_cpu_data; > /* > * Set PCI cacheline size to that of the highest level in the > * cache hierarchy. > @@ -38,6 +40,7 @@ static int __init pcibios_set_cache_line_size(void) > lsize = c->dcache.linesz; > lsize = c->scache.linesz ? : lsize; > lsize = c->tcache.linesz ? : lsize; > + preempt_enable(); > > BUG_ON(!lsize); > >