Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753334AbdHJUiF (ORCPT ); Thu, 10 Aug 2017 16:38:05 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:34828 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753180AbdHJUiD (ORCPT ); Thu, 10 Aug 2017 16:38:03 -0400 Date: Thu, 10 Aug 2017 15:38:01 -0500 From: Rob Herring To: Chris Packham Cc: gregory.clement@free-electrons.com, bp@alien8.de, jlu@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland , devicetree@vger.kernel.org Subject: Re: [RESEND PATCH 2/4] dt-bindings: add "reduced-width" property for Armada XP SDRAM controller Message-ID: <20170810203801.jz5hl5onqci275ef@rob-hp-laptop> References: <20170807014641.4003-1-chris.packham@alliedtelesis.co.nz> <20170807014641.4003-3-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170807014641.4003-3-chris.packham@alliedtelesis.co.nz> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1386 Lines: 32 On Mon, Aug 07, 2017 at 01:46:39PM +1200, Chris Packham wrote: > Some SoC implementations that use this controller have a reduced pin > count so the meaning of "full" and "half" with change. s/with/width/ ? > > Signed-off-by: Chris Packham > --- > .../bindings/memory-controllers/mvebu-sdram-controller.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt > index 89657d1d4cd4..3041868321c8 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt > @@ -13,6 +13,12 @@ Required properties: > - reg: a resource specifier for the register space, which should > include all SDRAM controller registers as per the datasheet. > > +Optional properties: > + - marvell,reduced-width: some SoCs that use this SDRAM controller have > + a reduced pin count. On such systems "full" width is 32-bits and > + "half" width is 16-bits. Set this property to indicate that the SoC > + used is such a system. Maybe you should just state what the width is. Or your compatible string should just be specific enough to know the width. Rob