Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753412AbdHJVij (ORCPT ); Thu, 10 Aug 2017 17:38:39 -0400 Received: from shards.monkeyblade.net ([184.105.139.130]:37682 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753374AbdHJVii (ORCPT ); Thu, 10 Aug 2017 17:38:38 -0400 Date: Thu, 10 Aug 2017 14:38:35 -0700 (PDT) Message-Id: <20170810.143835.350138228946748074.davem@davemloft.net> To: babu.moger@oracle.com Cc: sparclinux@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/4] Update memcpy, memset etc. for M7/M8 architectures From: David Miller In-Reply-To: <1502149972-61517-1-git-send-email-babu.moger@oracle.com> References: <1502149972-61517-1-git-send-email-babu.moger@oracle.com> X-Mailer: Mew version 6.7 on Emacs 25.2 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.5.12 (shards.monkeyblade.net [149.20.54.216]); Thu, 10 Aug 2017 14:38:37 -0700 (PDT) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1000 Lines: 27 From: Babu Moger Date: Mon, 7 Aug 2017 17:52:48 -0600 > This series of patches updates the memcpy, memset, copy_to_user, > copy_from_user etc for SPARC M7/M8 architecture. This doesn't build, you cannot assume the existence of "%ncc", it is a recent addition. Furthermore there is no need to ever use %ncc in v9 targetted code anyways. I'll fix that up, but this was a really disappointing build failure to hit. Meanwhile, two questions: 1) Is this also faster on T4 as well? If it is, we can just get rid of the T4 routines and use this on those chips as well. 2) There has been a lot of discussion and consideration put into how a memcpy/memset routine might be really great for the local cpu but overall pessimize performance for other cpus either locally on the same core (contention for physical resources such as ports to the store buffer and/or L3 cache) or on other cores. Has any such study been done into these issues wrt. this new code?