Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753276AbdHKPDg (ORCPT ); Fri, 11 Aug 2017 11:03:36 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:38445 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752631AbdHKPDe (ORCPT ); Fri, 11 Aug 2017 11:03:34 -0400 Date: Fri, 11 Aug 2017 08:03:29 -0700 User-Agent: K-9 Mail for Android In-Reply-To: <20170811132526.GD25147@Red> References: <20170810085129.20463-1-clabbe.montjoie@gmail.com> <20170810085129.20463-3-clabbe.montjoie@gmail.com> <20170811080543.GA25147@Red> <20170811081920.GB25147@Red> <20170811132526.GD25147@Red> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Subject: Re: [PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY To: Corentin Labbe , Chen-Yu Tsai , robh+dt@kernel.org, mark.rutland@arm.com CC: Russell King , Maxime Ripard , Giuseppe Cavallaro , alexandre.torgue@st.com, netdev , devicetree , linux-kernel , linux-arm-kernel , andrew@lunn.ch From: Florian Fainelli Message-ID: <302496B2-46F1-456D-A9A0-8257B5582695@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v7BF3eU9015591 Content-Length: 5031 Lines: 141 On August 11, 2017 6:25:26 AM PDT, Corentin Labbe wrote: >On Fri, Aug 11, 2017 at 04:22:11PM +0800, Chen-Yu Tsai wrote: >> On Fri, Aug 11, 2017 at 4:19 PM, Corentin Labbe >> wrote: >> > On Fri, Aug 11, 2017 at 04:11:13PM +0800, Chen-Yu Tsai wrote: >> >> On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe >> >> wrote: >> >> > On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote: >> >> >> Hi, >> >> >> >> >> >> On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe >> >> >> wrote: >> >> >> > This patch add the new phy-is-integrated property to the >internal PHY >> >> >> > node. >> >> >> > >> >> >> > Signed-off-by: Corentin Labbe >> >> >> > --- >> >> >> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + >> >> >> > 1 file changed, 1 insertion(+) >> >> >> > >> >> >> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> >> >> > index 4b599b5d26f6..54fc24e4c569 100644 >> >> >> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> >> >> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> >> >> > @@ -425,6 +425,7 @@ >> >> >> > reg = <1>; >> >> >> > clocks = <&ccu >CLK_BUS_EPHY>; >> >> >> > resets = <&ccu >RST_BUS_EPHY>; >> >> >> > + phy-is-integrated; >> >> >> >> >> >> You also need to "delete" this property at the board level for >> >> >> any board that has the external PHY at address <1>. Otherwise >> >> >> they will stop working. This is due to the internal and >external >> >> >> PHYs having the same path and node name in the device tree, so >> >> >> they are effectively the same node. >> >> >> >> >> >> ChenYu >> >> >> >> >> > >> >> > They have not the same name, ext_rgmii_phy vs int_mii_phy. >> >> >> >> That is just the label. The label plays no part in device tree >merging. The path >> >> >> >> /soc/ethernet@1c30000/mdio/ethernet-phy@1 >> >> >> >> is the same. You can look under >> >> >> >> /proc/device-tree/soc/ethernet@1c30000/mdio >> >> >> >> on the OrangePI Plus 2E or any other H3 board that uses an >> >> external PHY at address 1. >> >> >> >> ChenYu >> > >> > Since we get the phy node by phy-handle and not by path, I think >all should be good. >> >> You are not getting me. The fact that the two seemingly separate >> nodes are merged together means, whatever properties you put in >> the internal PHY node, also affect the external PHY node. Once >> compiled, they are the SAME node. > >Hello Rob, florian, mark > >Adding a delete property on all external ethernet-phy@1 is a bit >overkill, and I dont like the idea that nodes are merged. This is not exactly up to you that's just how DTC works. >What do you think about other possible solutions: >- Using integrated-phy@1 for the integrated PHY node name That might be okay although you are using now a seemingly non-standard unit name. >- Using a fake address like 31 (see patch below) You could also drop the address part in the unit name although we'd probably get a DTC warning for that. I suspect both of your solutions and what I mentioned above will be producing DTC warnings to some extent... Rob what do you think? > >If you have any other solution... > >Regards > >From fe39183946f7f4a6e21bce38fd8e4c1413012d68 Mon Sep 17 00:00:00 2001 >From: Corentin Labbe >Date: Fri, 11 Aug 2017 14:49:54 +0200 >Subject: [PATCH] ARM: sun8i: sunxi-h3-h5: Prevent merge of external and > integrated PHY > >Actually, some external and integrated PHY are merged due to same >dtnode >name "ethernet-phy@1". > >This is problematic when we will want to use the phy-is-integrated >property. (Need to delete it on all external PHY node) > >An easy solution is to set integrated PHY nodeaddresss at a fake one >that would never be used. >Since board makers currently only provides PHY at addresses 1 and 7, >we will use 31. > >Signed-off-by: Corentin Labbe >--- > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > >diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >index 54fc24e4c569..2110b0069e33 100644 >--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >@@ -420,7 +420,15 @@ > mdio: mdio { > #address-cells = <1>; > #size-cells = <0>; >- int_mii_phy: ethernet-phy@1 { >+ /* >+ * Using 31 permits to make a separation between >+ * this integrated PHY and external ones. >+ * Without it, external "ethernet-phy@1" will be >+ * merged with it (due to same dtnode name). >+ * Board makers currently only provides PHY at >+ * addresses 1 and 7. >+ */ >+ int_mii_phy: ethernet-phy@31 { > compatible = "ethernet-phy-ieee802.3-c22"; > reg = <1>; > clocks = <&ccu CLK_BUS_EPHY>; -- Florian