Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752311AbdHNRkn (ORCPT ); Mon, 14 Aug 2017 13:40:43 -0400 Received: from mga09.intel.com ([134.134.136.24]:49176 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750910AbdHNRkl (ORCPT ); Mon, 14 Aug 2017 13:40:41 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,374,1498546800"; d="scan'208";a="1182623427" Date: Mon, 14 Aug 2017 10:19:38 -0700 From: "Raj, Ashok" To: Ding Tianhong Cc: leedom@chelsio.com, bhelgaas@google.com, helgaas@kernel.org, werner@chelsio.com, ganeshgr@chelsio.com, asit.k.mallick@intel.com, patrick.j.cramer@intel.com, Suravee.Suthikulpanit@amd.com, Bob.Shaw@amd.com, l.stach@pengutronix.de, amira@mellanox.com, gabriele.paoloni@huawei.com, David.Laight@aculab.com, jeffrey.t.kirsher@intel.com, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, davem@davemloft.net, alexander.duyck@gmail.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linuxarm@huawei.com, ashok.raj@intel.com Subject: Re: [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Message-ID: <20170814171937.GA52656@otc-nc-03> References: <1502725499-11276-1-git-send-email-dingtianhong@huawei.com> <1502725499-11276-4-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1502725499-11276-4-git-send-email-dingtianhong@huawei.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2248 Lines: 51 On Mon, Aug 14, 2017 at 11:44:57PM +0800, Ding Tianhong wrote: > Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe > Root Port where Upstream Transaction Layer Packets with the Relaxed > Ordering Attribute clear are allowed to bypass earlier TLPs with > Relaxed Ordering set, it would cause Data Corruption, so we need > to disable Relaxed Ordering Attribute when Upstream TLPs to the > Root Port. > > Signed-off-by: Casey Leedom > Signed-off-by: Ding Tianhong > Acked-by: Alexander Duyck > Acked-by: Ashok Raj I can't ack this patch :-).. must be someone from AMD. Please remove my signature from this. > --- > drivers/pci/quirks.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index 1272f7e..1407604 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -4089,6 +4089,22 @@ static void quirk_relaxedordering_disable(struct pci_dev *dev) > quirk_relaxedordering_disable); > > /* > + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex > + * where Upstream Transaction Layer Packets with the Relaxed Ordering > + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering > + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules > + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 > + * November 10, 2010). As a result, on this platform we can't use Relaxed > + * Ordering for Upstream TLPs. > + */ > +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, > + quirk_relaxedordering_disable); > +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, > + quirk_relaxedordering_disable); > +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, > + quirk_relaxedordering_disable); > + > +/* > * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same > * values for the Attribute as were supplied in the header of the > * corresponding Request, except as explicitly allowed when IDO is used." > -- > 1.8.3.1 > >