Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753692AbdHOBmE (ORCPT ); Mon, 14 Aug 2017 21:42:04 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3083 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752985AbdHOBl5 (ORCPT ); Mon, 14 Aug 2017 21:41:57 -0400 Subject: Re: [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 To: "Raj, Ashok" References: <1502725499-11276-1-git-send-email-dingtianhong@huawei.com> <1502725499-11276-4-git-send-email-dingtianhong@huawei.com> <20170814171937.GA52656@otc-nc-03> CC: , , , , , , , , , , , , , , , , , , , , , , , , From: Ding Tianhong Message-ID: Date: Tue, 15 Aug 2017 09:40:27 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <20170814171937.GA52656@otc-nc-03> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5992511B.0007,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 776338a5d08846dbdfcbdd0413c46c0c Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2400 Lines: 62 On 2017/8/15 1:19, Raj, Ashok wrote: > On Mon, Aug 14, 2017 at 11:44:57PM +0800, Ding Tianhong wrote: >> Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe >> Root Port where Upstream Transaction Layer Packets with the Relaxed >> Ordering Attribute clear are allowed to bypass earlier TLPs with >> Relaxed Ordering set, it would cause Data Corruption, so we need >> to disable Relaxed Ordering Attribute when Upstream TLPs to the >> Root Port. >> >> Signed-off-by: Casey Leedom >> Signed-off-by: Ding Tianhong >> Acked-by: Alexander Duyck >> Acked-by: Ashok Raj > > I can't ack this patch :-).. must be someone from AMD. Please remove my > signature from this. > Sorry for funny mistake :) I will fix it. Ding >> --- >> drivers/pci/quirks.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c >> index 1272f7e..1407604 100644 >> --- a/drivers/pci/quirks.c >> +++ b/drivers/pci/quirks.c >> @@ -4089,6 +4089,22 @@ static void quirk_relaxedordering_disable(struct pci_dev *dev) >> quirk_relaxedordering_disable); >> >> /* >> + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex >> + * where Upstream Transaction Layer Packets with the Relaxed Ordering >> + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering >> + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules >> + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 >> + * November 10, 2010). As a result, on this platform we can't use Relaxed >> + * Ordering for Upstream TLPs. >> + */ >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> + >> +/* >> * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same >> * values for the Attribute as were supplied in the header of the >> * corresponding Request, except as explicitly allowed when IDO is used." >> -- >> 1.8.3.1 >> >> > > . >