Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751893AbdHPLi4 (ORCPT ); Wed, 16 Aug 2017 07:38:56 -0400 Received: from 5.mo3.mail-out.ovh.net ([87.98.178.36]:45511 "EHLO 5.mo3.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751584AbdHPLiz (ORCPT ); Wed, 16 Aug 2017 07:38:55 -0400 X-Greylist: delayed 16198 seconds by postgrey-1.27 at vger.kernel.org; Wed, 16 Aug 2017 07:38:55 EDT Subject: Re: [PATCH] i2c: aspeed: Retain delay/setup/hold values when configuring bus frequency To: Joel Stanley , Andrew Jeffery Cc: Ryan Chen , linux-aspeed@lists.ozlabs.org, Wolfram Sang , Benjamin Herrenschmidt , OpenBMC Maillist , Brendan Higgins , Linux Kernel Mailing List , linux-i2c@vger.kernel.org References: <20170815072102.23067-1-andrew@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <247768a3-074f-70ad-6132-39d1443ce210@kaod.org> Date: Wed, 16 Aug 2017 08:53:30 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Ovh-Tracer-Id: 17003058922318826484 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrleekgdduvdefucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2713 Lines: 56 On 08/16/2017 08:49 AM, Joel Stanley wrote: > On Tue, Aug 15, 2017 at 4:51 PM, Andrew Jeffery wrote: >> In addition to the base, low and high clock configuration, the AC timing >> register #1 on the AST2400 houses fields controlling: >> >> 1. tBUF: Minimum delay between Stop and Start conditions >> 2. tHDSTA: Hold time for the Start condition >> 3. tACST: Setup time for Start and Stop conditions, and hold time for the >> Repeated Start condition >> >> These values are defined in hardware on the AST2500 and therefore don't >> need to be set. >> >> aspeed_i2c_init_clk() was performing a direct write of the generated >> clock values rather than a read/mask/modify/update sequence to retain >> tBUF, tHDSTA and tACST, and therefore cleared the tBUF, tHDSTA and tACST >> fields on the AST2400. This resulted in a delay/setup/hold time of 1 >> base clock, which in some configurations is not enough for some devices >> (e.g. the MAX31785 fan controller, with an APB of 48MHz and a desired >> bus speed of 100kHz). >> >> Signed-off-by: Andrew Jeffery >> --- >> drivers/i2c/busses/i2c-aspeed.c | 9 ++++++++- >> 1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c >> index ee76e6dddc4b..284f8670dbeb 100644 >> --- a/drivers/i2c/busses/i2c-aspeed.c >> +++ b/drivers/i2c/busses/i2c-aspeed.c >> @@ -53,6 +53,9 @@ >> #define ASPEED_I2CD_MASTER_EN BIT(0) >> >> /* 0x04 : I2CD Clock and AC Timing Control Register #1 */ >> +#define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28) >> +#define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24) >> +#define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20) >> #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16 >> #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16) >> #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12 >> @@ -744,7 +747,11 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) >> u32 divisor, clk_reg_val; >> >> divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency); >> - clk_reg_val = bus->get_clk_reg_val(divisor); >> + clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); >> + clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK | >> + ASPEED_I2CD_TIME_THDSTA_MASK | >> + ASPEED_I2CD_TIME_TACST_MASK); > > Instead of keeping the u-boot values (which appear to be hard-coded), > should we instead put the known working values in the register? Yes. I was wondering where the initial setting was from on the AST400. C.