Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752613AbdHQDjO (ORCPT ); Wed, 16 Aug 2017 23:39:14 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4015 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752510AbdHQDjA (ORCPT ); Wed, 16 Aug 2017 23:39:00 -0400 Subject: Re: [PATCH v4 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver To: Mark Rutland References: <1500984642-204676-1-git-send-email-zhangshaokun@hisilicon.com> <1500984642-204676-5-git-send-email-zhangshaokun@hisilicon.com> <20170815110518.GE6090@leverpostej> CC: , , , , , From: Zhangshaokun Message-ID: <059720e3-e842-3e51-158d-3d36a2081bdd@hisilicon.com> Date: Thu, 17 Aug 2017 11:38:34 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <20170815110518.GE6090@leverpostej> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.74.221.148] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.59950FCC.0165,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 03b560f340931cef7c492a2f05f5b6cf Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2126 Lines: 90 Hi Mark, On 2017/8/15 19:05, Mark Rutland wrote: > On Tue, Jul 25, 2017 at 08:10:40PM +0800, Shaokun Zhang wrote: >> +/* HHA register definition */ >> +#define HHA_INT_MASK 0x0804 >> +#define HHA_INT_STATUS 0x0808 >> +#define HHA_INT_CLEAR 0x080C >> +#define HHA_PERF_CTRL 0x1E00 >> +#define HHA_EVENT_CTRL 0x1E04 >> +#define HHA_EVENT_TYPE0 0x1E80 >> +#define HHA_CNT0_LOWER 0x1F00 >> + >> +/* HHA has 16-counters and supports 0x50 events */ > > As with the L3C PMU, what exactly does this mean? > > Does this mean event IDs 0-0x4f are valid? > It is the same as L3C PMU and it is event IDs. > [...] > >> +static irqreturn_t hisi_hha_pmu_isr(int irq, void *dev_id) >> +{ >> + struct hisi_pmu *hha_pmu = dev_id; >> + struct perf_event *event; >> + unsigned long overflown; >> + u32 status; >> + int idx; >> + >> + /* Read HHA_INT_STATUS register */ >> + status = readl(hha_pmu->base + HHA_INT_STATUS); >> + if (!status) >> + return IRQ_NONE; >> + overflown = status; > > No need for the u32 temporary here. > Ok. > [....] > >> +static int hisi_hha_pmu_dev_probe(struct platform_device *pdev, >> + struct hisi_pmu *hha_pmu) >> +{ >> + struct device *dev = &pdev->dev; >> + int ret; >> + >> + ret = hisi_hha_pmu_init_data(pdev, hha_pmu); >> + if (ret) >> + return ret; >> + >> + /* Pick one core to use for cpumask attributes */ >> + cpumask_set_cpu(smp_processor_id(), &hha_pmu->cpus); >> + > > Why does this not have the usual event migration callbacks, across CPUs > in the same SCCL? > Sorry we missed this. Shall add CPU hotplug callbacks and handle the cpumask update and event migration. >> + ret = hisi_hha_pmu_init_irq(hha_pmu, pdev); >> + if (ret) >> + return ret; >> + >> + hha_pmu->name = devm_kasprintf(dev, GFP_KERNEL, "hisi_hha%u_%u", >> + hha_pmu->hha_uid, hha_pmu->sccl_id); > > As on the doc patch, this should be hierarchical. > Surely. Thanks, Shaokun > Thanks, > Mark > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > >