Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752111AbdHQK44 convert rfc822-to-8bit (ORCPT ); Thu, 17 Aug 2017 06:56:56 -0400 Received: from smtp-out4.electric.net ([192.162.216.186]:56400 "EHLO smtp-out4.electric.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750913AbdHQK4y (ORCPT ); Thu, 17 Aug 2017 06:56:54 -0400 From: David Laight To: "'Alex Williamson'" , Benjamin Herrenschmidt CC: Jike Song , Neo Jia , "kvm@vger.kernel.org" , Eric Auger , Alexey Kardashevskiy , Robin Murphy , Joerg Roedel , Kyle Mahlkuch , Vlad Tsyrklevich , "kvm-ppc@vger.kernel.org" , "iommu@lists.linux-foundation.org" , Yongji Xie , Kirti Wankhede , Mauricio Faria de Oliveira , Paul Mackerras , Bjorn Helgaas , Arvind Yadav , "linuxppc-dev@lists.ozlabs.org" , David Woodhouse , "linux-kernel@vger.kernel.org" , David Gibson Subject: RE: [RFC PATCH v5 0/5] vfio-pci: Add support for mmapping MSI-X table Thread-Topic: [RFC PATCH v5 0/5] vfio-pci: Add support for mmapping MSI-X table Thread-Index: AQHTFrCKY9aWZpUct0u3iOg3LSbxxKKIXcGQ Date: Thu, 17 Aug 2017 10:56:35 +0000 Message-ID: <063D6719AE5E284EB5DD2968C1650D6DD0059144@AcuExch.aculab.com> References: <20170807072548.3023-1-aik@ozlabs.ru> <8f5f7b82-3c10-7f39-b587-db4c4424f04c@ozlabs.ru> <20170815103717.3b64e10c@w520.home> <1502843749.4493.67.camel@kernel.crashing.org> <20170816105602.57fd1dcc@w520.home> In-Reply-To: <20170816105602.57fd1dcc@w520.home> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.99.200] Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-Outbound-IP: 156.67.243.126 X-Env-From: David.Laight@ACULAB.COM X-Proto: esmtps X-Revdns: X-HELO: AcuExch.aculab.com X-TLS: TLSv1:AES128-SHA:128 X-Authenticated_ID: X-PolicySMART: 3396946, 3397078 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 956 Lines: 23 From: Alex Williamson > Sent: 16 August 2017 17:56 ... > Firmware pissing match... Processors running with 8k or less page size > fall within the recommendations of the PCI spec for register alignment > of MMIO regions of the device and this whole problem becomes less of an > issue. Actually if qemu is causing the MSI-X table accesses to fault, why doesn't it just lie to the guest about the physical address of the MSI-X table? Then mmio access to anything in the same physical page will just work. It has already been pointed out that you can't actually police the interrupts that are raised without host hardware support. Actually, putting other vectors in the MSI-X table is boring, most drivers will ignore unexpected interrupts. Much more interesting are physical memory addresses and accessible IO addresses. Of course, a lot of boards have PCI master capability and can probably be persuaded to do writes to specific location anyway. David