Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752714AbdHQMIj (ORCPT ); Thu, 17 Aug 2017 08:08:39 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35452 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752722AbdHQMIf (ORCPT ); Thu, 17 Aug 2017 08:08:35 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C393C60708 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Boris Brezillon Cc: David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , Cyrille Pitchen , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Andy Gross , Archit Taneja , Sricharan R , Abhishek Sahu Subject: [PATCH v5 06/16] mtd: nand: qcom: erased codeword detection configuration Date: Thu, 17 Aug 2017 17:37:44 +0530 Message-Id: <1502971674-13810-7-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1502971674-13810-1-git-send-email-absahu@codeaurora.org> References: <1502971674-13810-1-git-send-email-absahu@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2802 Lines: 79 The NAND controller returns ECC failure during read of completely erased codeword. The NAND controller has hardware functionality to detect erased codeword in case of BCH ECC algorithm. The NAND_ERASED_CW_DETECT_CFG register controls the erased codeword/page detection controller. This register should be reset before every page read by setting and clearing bit 0 of NAND_ERASED_CW_DETECT_CFG. Reviewed-by: Archit Taneja Signed-off-by: Abhishek Sahu --- * Changes from v4: None drivers/mtd/nand/qcom_nandc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c index 9d55e8e..81cfce7 100644 --- a/drivers/mtd/nand/qcom_nandc.c +++ b/drivers/mtd/nand/qcom_nandc.c @@ -203,6 +203,11 @@ #define NAND_BAM_NWD BIT(1) /* Finish writing in the current BAM sgl and start writing in another BAM sgl */ #define NAND_BAM_NEXT_SGL BIT(2) +/* + * Erased codeword status is being used two times in single transfer so this + * flag will determine the current value of erased codeword status register + */ +#define NAND_ERASED_CW_SET BIT(4) /* * This data type corresponds to the BAM transaction which will be used for all @@ -281,6 +286,8 @@ struct nandc_regs { __le32 read_location2; __le32 read_location3; + __le32 erased_cw_detect_cfg_clr; + __le32 erased_cw_detect_cfg_set; }; /* @@ -810,6 +817,13 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first, if (first == NAND_FLASH_CMD) flow_control = true; + if (first == NAND_ERASED_CW_DETECT_CFG) { + if (flags & NAND_ERASED_CW_SET) + vaddr = ®s->erased_cw_detect_cfg_set; + else + vaddr = ®s->erased_cw_detect_cfg_clr; + } + if (first == NAND_EXEC_CMD) flags |= NAND_BAM_NWD; @@ -864,6 +878,9 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc) write_reg_dma(nandc, NAND_ADDR0, 2, 0); write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); } /* @@ -2264,6 +2281,10 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host) host->clrflashstatus = FS_READY_BSY_N; host->clrreadstatus = 0xc0; + nandc->regs->erased_cw_detect_cfg_clr = + cpu_to_le32(CLR_ERASED_PAGE_DET); + nandc->regs->erased_cw_detect_cfg_set = + cpu_to_le32(SET_ERASED_PAGE_DET); dev_dbg(nandc->dev, "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n", -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation