Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753117AbdHQNBX (ORCPT ); Thu, 17 Aug 2017 09:01:23 -0400 Received: from pandora.armlinux.org.uk ([78.32.30.218]:43462 "EHLO pandora.armlinux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751711AbdHQNBV (ORCPT ); Thu, 17 Aug 2017 09:01:21 -0400 Date: Thu, 17 Aug 2017 14:01:03 +0100 From: Russell King - ARM Linux To: Danilo Krummrich Cc: Linus Walleij , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linux Input , Dmitry Torokhov , devicetree@vger.kernel.org Subject: Re: [PATCH] serio: PS2 gpio bit banging driver for the serio bus Message-ID: <20170817130103.GR20805@n2100.armlinux.org.uk> References: <20170731222452.22887-1-danilokrummrich@dk-develop.de> <20170807182207.348762301bf3d7f8509b1bf7@dk-develop.de> <8e5e73575b3a70e0e60931698687471d@dk-develop.de> <20170817090908.GP20805@n2100.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1542 Lines: 31 On Thu, Aug 17, 2017 at 12:51:33PM +0200, Danilo Krummrich wrote: > That having the correct execution order is not enough on some buses because > of buffering is really something to be aware of, thanks again for pointing > this out. PCI guarantees the order of writes to a device, but there are situations on SoCs where you can't rely on that - for instance, if the writes go over different buses to different devices (eg, write to a peripheral vs write to an interrupt controller.) Even then, with interrupts delivered by message (eg, MSI) there's issues. > So for the scenario I was concerned about I would expect the irqchip driver > guarantees the write actually hits the the hardware (if necessary read it > back) before the function (disable_irq_nosync()) returns, is that correct? > Though, having the need should be very unlikely. Well, disable_irq_nosync() doesn't guarantee that the interrupt handler isn't running - a CPU may have just received the interrupt and is just entering the interrupt handler when disable_irq_nosync() returns. The hint is the "nosync" - there's no synchronisation. If you need to guarantee that the interrupt handler is not running, disable_irq() does that. By implication, however, disable_irq() can not be called from within the same interrupt handler for the interrupt that is being disabled. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up According to speedtest.net: 8.21Mbps down 510kbps up