Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753050AbdHQOO0 (ORCPT ); Thu, 17 Aug 2017 10:14:26 -0400 Received: from hs01.dk-develop.de ([213.136.71.231]:41162 "EHLO hs01.dk-develop.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752484AbdHQOOY (ORCPT ); Thu, 17 Aug 2017 10:14:24 -0400 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 17 Aug 2017 16:14:23 +0200 From: Danilo Krummrich To: Russell King - ARM Linux Cc: Linus Walleij , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linux Input , Dmitry Torokhov , devicetree@vger.kernel.org Subject: Re: [PATCH] serio: PS2 gpio bit banging driver for the serio bus In-Reply-To: <20170817130103.GR20805@n2100.armlinux.org.uk> References: <20170731222452.22887-1-danilokrummrich@dk-develop.de> <20170807182207.348762301bf3d7f8509b1bf7@dk-develop.de> <8e5e73575b3a70e0e60931698687471d@dk-develop.de> <20170817090908.GP20805@n2100.armlinux.org.uk> <20170817130103.GR20805@n2100.armlinux.org.uk> Message-ID: <52be16427347cefff9238902146df110@dk-develop.de> User-Agent: Roundcube Webmail/1.3.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1760 Lines: 43 On 2017-08-17 15:01, Russell King - ARM Linux wrote: > On Thu, Aug 17, 2017 at 12:51:33PM +0200, Danilo Krummrich wrote: >> That having the correct execution order is not enough on some buses >> because >> of buffering is really something to be aware of, thanks again for >> pointing >> this out. > > PCI guarantees the order of writes to a device, but there are > situations > on SoCs where you can't rely on that - for instance, if the writes go > over different buses to different devices (eg, write to a peripheral > vs write to an interrupt controller.) > > Even then, with interrupts delivered by message (eg, MSI) there's > issues. > >> So for the scenario I was concerned about I would expect the irqchip >> driver >> guarantees the write actually hits the the hardware (if necessary read >> it >> back) before the function (disable_irq_nosync()) returns, is that >> correct? >> Though, having the need should be very unlikely. > > Well, disable_irq_nosync() doesn't guarantee that the interrupt handler > isn't running - a CPU may have just received the interrupt and is just > entering the interrupt handler when disable_irq_nosync() returns. The > hint is the "nosync" - there's no synchronisation. If you need to > guarantee that the interrupt handler is not running, disable_irq() does > that. By implication, however, disable_irq() can not be called from > within the same interrupt handler for the interrupt that is being > disabled. > Thanks again, I'm aware of that. As in my case the code could be called from atomic context disable_irq() is not an option. My main point is if it can be assumed that after disable_irq_nosync() returns it is guaranteed, by convention, that the hardware was hit. But I really would think so.