Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932113AbdHRAm6 (ORCPT ); Thu, 17 Aug 2017 20:42:58 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4488 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932069AbdHRAm4 (ORCPT ); Thu, 17 Aug 2017 20:42:56 -0400 Subject: Re: [PATCH net v2 2/2] net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag To: "Tantilov, Emil S" , "davem@davemloft.net" , "Kirsher, Jeffrey T" , "keescook@chromium.org" , "linux-kernel@vger.kernel.org" , "sparclinux@vger.kernel.org" , "intel-wired-lan@lists.osuosl.org" , "alexander.duyck@gmail.com" , "netdev@vger.kernel.org" , "linuxarm@huawei.com" References: <1502940316-13384-1-git-send-email-dingtianhong@huawei.com> <1502940316-13384-3-git-send-email-dingtianhong@huawei.com> <87618083B2453E4A8714035B62D67992B4094F7A@FMSMSX105.amr.corp.intel.com> From: Ding Tianhong Message-ID: <2a7fc27b-c2f4-a7a1-9318-3a93531e7670@huawei.com> Date: Fri, 18 Aug 2017 08:39:23 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <87618083B2453E4A8714035B62D67992B4094F7A@FMSMSX105.amr.corp.intel.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.59963749.0150,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 88f1af0efd0c87184d1bcedb23a4159d Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1016 Lines: 39 On 2017/8/17 22:17, Tantilov, Emil S wrote: >> ret_val = ixgbe_start_hw_generic(hw); >> >> -#ifndef CONFIG_SPARC >> - /* Disable relaxed ordering */ >> - for (i = 0; ((i < hw->mac.max_tx_queues) && >> - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { >> - regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); >> - regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; >> - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); >> - } >> + if (!pcie_relaxed_ordering_enabled(adapter->pdev)) { > > As Alex mentioned there is no need for this check in any form. > > The HW defaults to Relaxed Ordering enabled unless it is disabled in > the PCIe Device Control Register. So the above logic is already done by HW. > > All you have to do is strip the code disabling relaxed ordering. > Hi Tantilov: I misunderstood Alex's suggestion, But I still couldn't find the logic where the HW disable the Relaxed Ordering when the PCIe Device Control Register disable it, can you point it out? Thanks Ding > Thanks, > Emil > > > . >