Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753942AbdHRA5A (ORCPT ); Thu, 17 Aug 2017 20:57:00 -0400 Received: from mga11.intel.com ([192.55.52.93]:6399 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752872AbdHRA45 (ORCPT ); Thu, 17 Aug 2017 20:56:57 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,390,1498546800"; d="scan'208";a="141694944" From: "Ong, Hean Loong" To: "robh@kernel.org" CC: "linux-kernel@vger.kernel.org" , "Ong@rob-hp-laptop" , "rdunlap@infradead.org" , "devicetree@vger.kernel.org" , "Vetter, Daniel" , "dri-devel@lists.freedesktop.org" , "dinguyen@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "laurent.pinchart@ideasonboard.com" Subject: Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite Thread-Topic: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite Thread-Index: AQHTEm4QlFD4GmEfiU29ycNRHdN0GaKILkgAgACggQA= Date: Fri, 18 Aug 2017 00:56:54 +0000 Message-ID: <1503017812.2075.1.camel@intel.com> References: <1502434187-6407-1-git-send-email-hean.loong.ong@intel.com> <1502434187-6407-2-git-send-email-hean.loong.ong@intel.com> <20170817152147.d4bqny5wmrexh3bu@rob-hp-laptop> In-Reply-To: <20170817152147.d4bqny5wmrexh3bu@rob-hp-laptop> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.226.242.7] Content-Type: text/plain; charset="utf-8" Content-ID: <1CD615ECD28AA245B0408CC6A85BB594@intel.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v7I0v5w5019879 Content-Length: 1468 Lines: 51 On Thu, 2017-08-17 at 10:22 -0500, Rob Herring wrote: > On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote: > > > > From: Ong Hean Loong > "dt-bindings: display: ..." for the subject. With that, > > Acked-by: Rob Herring > > > > > > > Device tree binding for Intel FPGA Video and Image > > Processing Suite. The binding involved would be generated > > from the Altera (Intel) Qsys system. The bindings would > > set the max width, max height, buts per pixel and memory > > port width. The device tree binding only supports the Intel > > Arria10 devkit and its variants. Vendor name retained as > > altr. > > > > Signed-off-by: Ong, Hean Loong > > --- > > V6: > > Fix comments for description > A completely useless version history. You should describe the diff  > between versions. > Noted. Would make the necessary changes > > > > > > V5: > > *Fix comments on description > > *remove bindings for bits per symbol as it has only one value which > > is 8 > > > > V4: > > *Fix comments on description > > > > V3: > > *Fix comments on description > > > > V2: > > *Fix comments on description > > > > V1: > > *Fix comments on description > > --- > > --- > >  .../devicetree/bindings/display/altr,vip-fb2.txt   | 42 > > ++++++++++++++++++++++ > >  1 file changed, 42 insertions(+) > >  create mode 100644 > > Documentation/devicetree/bindings/display/altr,vip-fb2.txt