Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753088AbdHRNRX (ORCPT ); Fri, 18 Aug 2017 09:17:23 -0400 Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:55773 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752954AbdHRNPz (ORCPT ); Fri, 18 Aug 2017 09:15:55 -0400 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit MIME-Version: 1.0 From: Ben Hutchings To: linux-kernel@vger.kernel.org, stable@vger.kernel.org CC: akpm@linux-foundation.org, "Marc Zyngier" , "Christoffer Dall" Date: Fri, 18 Aug 2017 14:13:20 +0100 Message-ID: X-Mailer: LinuxStableQueue (scripts by bwh) Subject: [PATCH 3.16 102/134] arm64: KVM: Fix decoding of Rt/Rt2 when trapping AArch32 CP accesses In-Reply-To: X-SA-Exim-Connect-IP: 82.70.136.246 X-SA-Exim-Mail-From: ben@decadent.org.uk X-SA-Exim-Scanned: No (on shadbolt.decadent.org.uk); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2474 Lines: 76 3.16.47-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Marc Zyngier commit c667186f1c01ca8970c785888868b7ffd74e51ee upstream. Our 32bit CP14/15 handling inherited some of the ARMv7 code for handling the trapped system registers, completely missing the fact that the fields for Rt and Rt2 are now 5 bit wide, and not 4... Let's fix it, and provide an accessor for the most common Rt case. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall [bwh: Backported to 3.16: - Use literal numbers in kvm_vcpu_sys_get_rt() - Adjust context] Signed-off-by: Ben Hutchings --- arch/arm64/include/asm/kvm_emulate.h | 6 ++++++ arch/arm64/kvm/sys_regs.c | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -187,6 +187,12 @@ static inline u8 kvm_vcpu_trap_get_fault return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC_TYPE; } +static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) +{ + u32 esr = kvm_vcpu_get_hsr(vcpu); + return (esr >> 5) & 0x1f; +} + static inline unsigned long kvm_vcpu_get_mpidr(struct kvm_vcpu *vcpu) { return vcpu_sys_reg(vcpu, MPIDR_EL1); --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -504,12 +504,12 @@ int kvm_handle_cp15_64(struct kvm_vcpu * { struct sys_reg_params params; u32 hsr = kvm_vcpu_get_hsr(vcpu); - int Rt2 = (hsr >> 10) & 0xf; + int Rt2 = (hsr >> 10) & 0x1f; params.is_aarch32 = true; params.is_32bit = false; params.CRm = (hsr >> 1) & 0xf; - params.Rt = (hsr >> 5) & 0xf; + params.Rt = kvm_vcpu_sys_get_rt(vcpu); params.is_write = ((hsr & 1) == 0); params.Op0 = 0; @@ -554,7 +554,7 @@ int kvm_handle_cp15_32(struct kvm_vcpu * params.is_aarch32 = true; params.is_32bit = true; params.CRm = (hsr >> 1) & 0xf; - params.Rt = (hsr >> 5) & 0xf; + params.Rt = kvm_vcpu_sys_get_rt(vcpu); params.is_write = ((hsr & 1) == 0); params.CRn = (hsr >> 10) & 0xf; params.Op0 = 0; @@ -629,7 +629,7 @@ int kvm_handle_sys_reg(struct kvm_vcpu * params.CRn = (esr >> 10) & 0xf; params.CRm = (esr >> 1) & 0xf; params.Op2 = (esr >> 17) & 0x7; - params.Rt = (esr >> 5) & 0x1f; + params.Rt = kvm_vcpu_sys_get_rt(vcpu); params.is_write = !(esr & 1); return emulate_sys_reg(vcpu, ¶ms);