Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932592AbdHVLh0 (ORCPT ); Tue, 22 Aug 2017 07:37:26 -0400 Received: from mga11.intel.com ([192.55.52.93]:2517 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932427AbdHVLhZ (ORCPT ); Tue, 22 Aug 2017 07:37:25 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,412,1498546800"; d="scan'208";a="892933402" Message-ID: <1503401841.25945.51.camel@linux.intel.com> Subject: Re: [PATCH 3/3] ACPI / PMIC: Add opregion driver for Intel Dollar Cove TI PMIC From: Andy Shevchenko To: Takashi Iwai Cc: linux-kernel@vger.kernel.org, Lee Jones , Dmitry Torokhov , "Rafael J . Wysocki" , Mika Westerberg , Johannes Stezenbach , linux-input@vger.kernel.org, linux-acpi@vger.kernel.org Date: Tue, 22 Aug 2017 14:37:21 +0300 In-Reply-To: References: <20170822055710.26515-1-tiwai@suse.de> <20170822055710.26515-4-tiwai@suse.de> <1503395915.25945.48.camel@linux.intel.com> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1951 Lines: 59 On Tue, 2017-08-22 at 13:01 +0200, Takashi Iwai wrote: > On Tue, 22 Aug 2017 12:25:12 +0200, > Takashi Iwai wrote: > > > > On Tue, 22 Aug 2017 11:58:35 +0200, > > Andy Shevchenko wrote: > > > > > > On Tue, 2017-08-22 at 07:57 +0200, Takashi Iwai wrote: > > > > This patch adds the opregion driver for Dollar Cove TI PMIC on > > > > Intel > > > > Cherry Trail devices.  The patch is based on the original work > > > > by > > > > Intel, found at: > > > >       https://github.com/01org/ProductionKernelQuilts > > > > with many cleanups and rewrites. > > > > > > > > The driver is currently provided only as built-in to follow > > > > other > > > > PMIC opregion drivers convention. > > > > > > > > The re-enumeration of devices at probe is required for fixing > > > > the > > > > issues on HP x2 210 G2.  See bug#195689. > > > > > > > > > > > > +static int dc_ti_pmic_get_raw_temp(struct regmap *regmap, int > > > > reg) > > > > +{ > > > > + int temp_l, temp_h; > > > > + > > > > + if (regmap_read(regmap, reg, &temp_l) || > > > > +     regmap_read(regmap, reg - 1, &temp_h)) > > > > + return -EIO; > > > > + > > > > + return temp_l | (temp_h & 0x3) << 8; > > > > +} > > > > > > I'm not sure I understand this "- 1" part along with choice of l > > > and h > > > suffixes. > > > > > > Does it mean the register is big endian? > > > > Good point, I need to check the original code and the values. > > It's really big-endian, the order is hi:lo. > > But, admittedly, the temperature code hasn't been tested, and it's > possibly missing something.  So I'm fine to drop that part in the > first version, too. I don't know if regmap allows you to define registers with different sizes for same chip, perhaps it would make sense to start register from hi part (and not doing non-intuitive "- 1", or maybe "+ 1" instead) and mark it in comment that is BE16. -- Andy Shevchenko Intel Finland Oy