Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751337AbdHXHFT (ORCPT ); Thu, 24 Aug 2017 03:05:19 -0400 Received: from mail-db5eur01on0077.outbound.protection.outlook.com ([104.47.2.77]:45184 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751263AbdHXHFQ (ORCPT ); Thu, 24 Aug 2017 03:05:16 -0400 From: "A.s. Dong" To: "A.s. Dong" , "linux-clk@vger.kernel.org" , Stephen Boyd CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "dongas86@gmail.com" , "shawnguo@kernel.org" , Anson Huang , Jacky Bai Subject: RE: [PATCH V2 00/10] clk: add imx7ulp clk support Thread-Topic: [PATCH V2 00/10] clk: add imx7ulp clk support Thread-Index: AQHS+83NWQVyDNLuf0yAGnXwSm7qdqJlfgFwgC3YPdA= Date: Thu, 24 Aug 2017 07:05:12 +0000 Message-ID: References: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-originating-ip: [192.158.241.86] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM3PR04MB0680;6:rAWCr5fFbbDtISYU74umlp8bHhSERDT9rSyo/QKqhZFEVt6Jd6wv1sTkRya7XbY6T+GTlzCcU1p+7tnt9r1rMyP5MiqNz1xiEhuezHGUFhjZDPi7N5qRd+0kOUn4yUVepch3j2u9MJ2I1SDM/sOAC6EvDV0fdjqxIkRpyYUT00Mg82h24xNYPMvDkjPkbD8K94MggM0UX3wmyTuDADGGOf0c6kr3NwZProK3Y2Jdv+Lmiq5qHJaBEIh/OfEKovPBzP1xll/jnaJsAPI0llsgrMCergzWX+DhN5IxjGatr75SJx/6S095x/KWYh1UkFsqq8tKsK47lRjo10zwVp8HLQ==;5:xp1knrXC4HsZASZuBsAAmByKiP4eklAx7BV4mnWJFJ90EqW1G5cmsdwrXM/iWyXXaR0P3Mox6oyl8GmtX/Bp/qOdCahVolK1aOcgzyQIQIVYqTaJzBdjcE2zFMFPkkC4d8Na/2CWIXPVY/OlyKPwbQ==;24:Ep4CXAHvCcul0mPFNm5OF47+oVWnwEBrcWFwzCzCTZCkoz3Fl6RJdv1PS8tA3m35Spx9fChitlsVlIpkLuzaOXrC3+rkspl/sycgApoloRM=;7:uutwcVLOnfsp5ITqNIzDWQW45eJl6+BpkKYt1BKiDSizE0M+jkpSAr4+tMWK7hZijN0uUvdz3wroT+RZLdddAAN9zsmJc6JB4vx6vf/QoV6j1gRyAr28fNLMZjthfsvDM/toOxrGUu8gVS/C4b4jMaxxrh1+4xo6/gKDaflTpUzH7aTrUHdp/iEIMrrDryhYupSrgOuqKtUHVFZ2e+EyQT/SIbKLfb3ttwP2NBgFsnA= x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-forefront-antispam-report: SFV:SKI;SCL:-1;SFV:NSPM;SFS:(10009020)(6009001)(39860400002)(189002)(13464003)(54534003)(199003)(377454003)(3846002)(102836003)(8936002)(6116002)(97736004)(8676002)(68736007)(53936002)(39060400002)(25786009)(6246003)(33656002)(6506006)(2900100001)(7736002)(14454004)(305945005)(6436002)(5250100002)(99286003)(3660700001)(55016002)(101416001)(81156014)(7696004)(50986999)(2501003)(189998001)(229853002)(3280700002)(54356999)(478600001)(105586002)(54906002)(74316002)(53546010)(66066001)(76176999)(2906002)(81166006)(106356001)(86362001)(4326008)(9686003)(5660300001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR04MB0680;H:AM3PR04MB306.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; x-ms-office365-filtering-correlation-id: 02edc265-bfc7-4d2a-207e-08d4eabe7761 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(48565401081)(300000503095)(300135400095)(2017052603196)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);SRVR:AM3PR04MB0680; x-ms-traffictypediagnostic: AM3PR04MB0680: x-exchange-antispam-report-test: UriScan:(9452136761055)(185117386973197)(258649278758335); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(100000703101)(100105400095)(6055026)(6041248)(20161123555025)(20161123560025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(20161123558100)(20161123562025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);SRVR:AM3PR04MB0680;BCL:0;PCL:0;RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);SRVR:AM3PR04MB0680; x-forefront-prvs: 04097B7F7F spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Aug 2017 07:05:13.2216 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB0680 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v7O75OFX014602 Content-Length: 4321 Lines: 103 > -----Original Message----- > From: A.s. Dong > Sent: Wednesday, July 26, 2017 10:57 AM > To: A.s. Dong; linux-clk@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > sboyd@codeaurora.org; mturquette@baylibre.com; dongas86@gmail.com; > shawnguo@kernel.org; Anson Huang; Jacky Bai > Subject: RE: [PATCH V2 00/10] clk: add imx7ulp clk support > > Ping... > Gently ping again... Hi Stephen, This has been more there without comments for more than one month. Would you help review when you're available later? Regards Dong Aisheng > > -----Original Message----- > > From: Dong Aisheng [mailto:aisheng.dong@nxp.com] > > Sent: Thursday, July 13, 2017 7:47 PM > > To: linux-clk@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org; > > linux-arm-kernel@lists.infradead.org; > > sboyd@codeaurora.org; mturquette@baylibre.com; A.s. Dong; > > dongas86@gmail.com; shawnguo@kernel.org; Anson Huang; Jacky Bai > > Subject: [PATCH V2 00/10] clk: add imx7ulp clk support > > > > This patch series intends to add imx7ulp clk support. > > > > i.MX7ULP Clock functions are under joint control of the System Clock > > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > > Core Mode Controller (CMC)1 blocks > > > > The clocking scheme provides clear separation between M4 domain and A7 > > domain. Except for a few clock sources shared between two domains, > > such as the System Oscillator clock, the Slow IRC (SIRC), and and the > > Fast IRC clock (FIRCLK), clock sources and clock management are > > separated and contained within each domain. > > > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > > > Note: this series only adds A7 clock domain support as M4 clock domain > > will be handled by M4 seperately. > > > > Change Log: > > v1->v2: > > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > > * use clk_hw apis to register clocks > > * use of_clk_add_hw_provider > > * split the clocks register process into two parts: early part for > > possible > > timers clocks registered by CLK_OF_DECLARE_DRIVER and the later > > part for > > the left normal peripheral clocks registered by a platform driver. > > > > Dong Aisheng (10): > > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > > clk: reparent orphans after critical clocks enabled > > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > > clk: imx: add pllv4 support > > clk: imx: add pfdv2 support > > clk: imx: add composite clk support > > dt-bindings: clock: add imx7ulp clock binding doc > > clk: imx: make mux parent strings const > > clk: imx: implement new clk_hw based APIs > > clk: imx: add imx7ulp clk driver > > > > .../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++ > > drivers/clk/clk-divider.c | 100 ++++++++- > > drivers/clk/clk-fractional-divider.c | 10 + > > drivers/clk/clk.c | 39 ++-- > > drivers/clk/imx/Makefile | 6 +- > > drivers/clk/imx/clk-busy.c | 2 +- > > drivers/clk/imx/clk-composite.c | 90 ++++++++ > > drivers/clk/imx/clk-fixup-mux.c | 2 +- > > drivers/clk/imx/clk-imx7ulp.c | 245 > > +++++++++++++++++++++ > > drivers/clk/imx/clk-pfdv2.c | 207 > > +++++++++++++++++ > > drivers/clk/imx/clk-pllv4.c | 188 > ++++++++++++++++ > > drivers/clk/imx/clk.c | 22 ++ > > drivers/clk/imx/clk.h | 92 +++++++- > > include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++ > > include/linux/clk-provider.h | 17 ++ > > 15 files changed, 1159 insertions(+), 31 deletions(-) create mode > > 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > create mode 100644 drivers/clk/imx/clk-composite.c create mode > > 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 > > drivers/clk/imx/clk- pfdv2.c create mode 100644 > > drivers/clk/imx/clk-pllv4.c create mode > > 100644 include/dt-bindings/clock/imx7ulp-clock.h > > > > -- > > 2.7.4