Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932986AbdHYN5L (ORCPT ); Fri, 25 Aug 2017 09:57:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:52948 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756337AbdHYN5J (ORCPT ); Fri, 25 Aug 2017 09:57:09 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B25D92156A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=helgaas@kernel.org Date: Fri, 25 Aug 2017 08:57:06 -0500 From: Bjorn Helgaas To: Brian Norris Cc: Jeffy Chen , linux-kernel@vger.kernel.org, bhelgaas@google.com, shawn.lin@rock-chips.com, dianders@chromium.org, devicetree@vger.kernel.org, Heiko Stuebner , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 3/4] dt-bindings: PCI: rockchip: Add support for pcie wake irq Message-ID: <20170825135706.GB1304@bhelgaas-glaptop.roam.corp.google.com> References: <20170822031934.8675-1-jeffy.chen@rock-chips.com> <20170822031934.8675-4-jeffy.chen@rock-chips.com> <20170824165353.GL31858@bhelgaas-glaptop.roam.corp.google.com> <20170825021132.GA104845@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170825021132.GA104845@google.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2150 Lines: 48 On Thu, Aug 24, 2017 at 07:11:32PM -0700, Brian Norris wrote: > On Thu, Aug 24, 2017 at 11:53:54AM -0500, Bjorn Helgaas wrote: > > On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: > > > Signed-off-by: Jeffy Chen > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > > index 5678be82530d..9f6504129e80 100644 > > > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > > @@ -20,10 +20,13 @@ Required properties: > > > - msi-map: Maps a Requester ID to an MSI controller and associated > > > msi-specifier data. See ./pci-msi.txt > > > - interrupts: Three interrupt entries must be specified. > > > -- interrupt-names: Must include the following names > > > - - "sys" > > > - - "legacy" > > > - - "client" > > > +- interrupt-names: Include the following names > > > + Required: > > > + - "sys" > > > + - "legacy" > > > + - "client" > > > + Optional: > > > + - "wake" > > > > Why is there no other PCI binding that includes "wake" as an > > interrupt-name? This feels like something that should be fairly > > common across host controllers. I don't want a Rockport-specific > > s/port/chip/ :) I visited Rockport this summer, guess I had it on the brain :) > > DT description if it could be made more general. > > I'm not sure we can really answer that question ("why do no other PCI > bindings have this?"). But one guess would be that every other > controller uses only beacon wake. > > It would be OK with me if we made a blanket statement that a controller > with a "wake" interrupt means PCI WAKE# (per the specification). It's > possible this could even be stuck into some generic PCI/DT code > eventually. (I don't think we have a really good place for this today.) I'd just like every controller that uses WAKE# to use the same name in DT. Maybe all that means for now is mentioning it in Documentation/devicetree/bindings/pci/pci.txt instead of (or in addition to) Documentation/devicetree/bindings/pci/rockchip-pcie.txt