Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754121AbdH1IOj (ORCPT ); Mon, 28 Aug 2017 04:14:39 -0400 Received: from mail.linuxfoundation.org ([140.211.169.12]:34808 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754105AbdH1IOg (ORCPT ); Mon, 28 Aug 2017 04:14:36 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Laurent Pinchart , Thong Ho , Nhan Nguyen Subject: [PATCH 4.4 26/53] drm: rcar-du: lvds: Rename PLLEN bit to PLLON Date: Mon, 28 Aug 2017 10:05:31 +0200 Message-Id: <20170828080518.830076148@linuxfoundation.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170828080517.599193891@linuxfoundation.org> References: <20170828080517.599193891@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1425 Lines: 43 4.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Laurent Pinchart commit 82e7c5e4964545352accff4b44bbcaa2c38e7fc1 upstream. The bit is named PLLON in the datasheet, rename it. Signed-off-by: Laurent Pinchart Signed-off-by: Thong Ho Signed-off-by: Nhan Nguyen Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 2 +- drivers/gpu/drm/rcar-du/rcar_lvds_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c @@ -102,7 +102,7 @@ static int rcar_du_lvdsenc_start(struct /* Turn the PLL on, wait for the startup delay, and turn the output * on. */ - lvdcr0 |= LVDCR0_PLLEN; + lvdcr0 |= LVDCR0_PLLON; rcar_lvds_write(lvds, LVDCR0, lvdcr0); usleep_range(100, 150); --- a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h @@ -18,7 +18,7 @@ #define LVDCR0_DMD (1 << 12) #define LVDCR0_LVMD_MASK (0xf << 8) #define LVDCR0_LVMD_SHIFT 8 -#define LVDCR0_PLLEN (1 << 4) +#define LVDCR0_PLLON (1 << 4) #define LVDCR0_BEN (1 << 2) #define LVDCR0_LVEN (1 << 1) #define LVDCR0_LVRES (1 << 0)