Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751790AbdH1OVz (ORCPT ); Mon, 28 Aug 2017 10:21:55 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:55360 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751286AbdH1OVT (ORCPT ); Mon, 28 Aug 2017 10:21:19 -0400 From: Amelie Delaunay To: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , John Youn CC: , , , , Benjamin Gaignard , Amelie Delaunay Subject: [PATCHv2 3/7] ARM: dts: stm32: Add USB HS support for STM32F746 MCU Date: Mon, 28 Aug 2017 16:20:14 +0200 Message-ID: <1503930018-536-4-git-send-email-amelie.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503930018-536-1-git-send-email-amelie.delaunay@st.com> References: <1503930018-536-1-git-send-email-amelie.delaunay@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.20.5] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-08-28_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2254 Lines: 76 This patch adds the USB pins and nodes for USB HS core on STM32F746 SoC. Signed-off-by: Amelie Delaunay --- arch/arm/boot/dts/stm32f746.dtsi | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 4506eb9..5d0cc72 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -361,6 +361,46 @@ bias-disable; }; }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs@1 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; }; crc: crc@40023000 { @@ -380,6 +420,15 @@ assigned-clocks = <&rcc 1 CLK_HSE_RTC>; assigned-clock-rates = <1000000>; }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; + clock-names = "otg"; + status = "disabled"; + }; }; }; -- 2.7.4