Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751959AbdH1SUq (ORCPT ); Mon, 28 Aug 2017 14:20:46 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:37357 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751284AbdH1SUn (ORCPT ); Mon, 28 Aug 2017 14:20:43 -0400 Date: Mon, 28 Aug 2017 20:20:39 +0200 From: Christoffer Dall To: Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Christoffer Dall , Thomas Gleixner , Jason Cooper , Eric Auger , Shanker Donthineni , Mark Rutland , Shameerali Kolothum Thodi Subject: Re: [PATCH v3 54/59] KVM: arm/arm64: GICv4: Enable virtual cpuif if VLPIs can be delivered Message-ID: <20170828182039.GO24649@cbox> References: <20170731172637.29355-1-marc.zyngier@arm.com> <20170731172637.29355-55-marc.zyngier@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170731172637.29355-55-marc.zyngier@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1571 Lines: 43 On Mon, Jul 31, 2017 at 06:26:32PM +0100, Marc Zyngier wrote: > In order for VLPIs to be delivered to the guest, we must make > sure that the cpuif is always enabled, irrespective of the > presence of virtual interrupt in the LRs. > > Signed-off-by: Marc Zyngier > --- > virt/kvm/arm/hyp/vgic-v3-sr.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c > index 91728faa13fd..f5c3d6d7019e 100644 > --- a/virt/kvm/arm/hyp/vgic-v3-sr.c > +++ b/virt/kvm/arm/hyp/vgic-v3-sr.c > @@ -258,7 +258,8 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu) > cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0); > } > } else { > - if (static_branch_unlikely(&vgic_v3_cpuif_trap)) > + if (static_branch_unlikely(&vgic_v3_cpuif_trap) || > + cpu_if->its_vpe.its_vm) > write_gicreg(0, ICH_HCR_EL2); > > cpu_if->vgic_elrsr = 0xffff; > @@ -337,9 +338,11 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) > /* > * If we need to trap system registers, we must write > * ICH_HCR_EL2 anyway, even if no interrupts are being > - * injected, > + * injected. Same thing if GICv4 is used, as VLPI > + * delivery is gated by ICH_HCR_EL2.En. > */ > - if (static_branch_unlikely(&vgic_v3_cpuif_trap)) > + if (static_branch_unlikely(&vgic_v3_cpuif_trap) || > + cpu_if->its_vpe.its_vm) > write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); > } > > -- > 2.11.0 > Acked-by: Christoffer Dall