Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751349AbdH2U1C (ORCPT ); Tue, 29 Aug 2017 16:27:02 -0400 Received: from mail-out-2.itc.rwth-aachen.de ([134.130.5.47]:30232 "EHLO mail-out-2.itc.rwth-aachen.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750909AbdH2U1B (ORCPT ); Tue, 29 Aug 2017 16:27:01 -0400 X-IronPort-AV: E=Sophos;i="5.41,445,1498514400"; d="scan'208";a="10845606" From: =?UTF-8?q?Stefan=20Br=C3=BCns?= To: CC: , , Maxime Ripard , Chen-Yu Tsai , Rob Herring Subject: [RESEND PATCH 0/2] Enable SPI on A64/Pine64 Date: Tue, 29 Aug 2017 22:26:50 +0200 Message-ID: <20170829202652.5476-1-stefan.bruens@rwth-aachen.de> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [92.224.122.214] X-ClientProxiedBy: rwthex-s2-b.rwth-ad.de (2002:8682:1a9b::8682:1a9b) To rwthex-w2-b.rwth-ad.de (2002:8682:1a9f::8682:1a9f) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 817 Lines: 22 The A64 SPI controller is compatible to the H3/H5 controller, i.e. same registers and same queue depth. The Pine64 exposes both controllers on the PI-2 and Euler connectors. Tested/verified with logic analyser and spidev_test using MOSI/MISO loopback. Note: spi0 on the A64 may conflict with the eMMC controller, as the MISO pin is also used for the HS400 eMMC data strobe. This is only a concern if the board uses eMMC (does not apply to the Pine64) *and* is using HS400 mode. The same pin conflict exists for the H5. Stefan Brüns (2): arm64: allwinner: a64: add SPI nodes arm64: allwinner: pine64: Enable spi0/spi1 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 +++++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 ++++++++++++++++++++++ 2 files changed, 48 insertions(+) -- 2.14.1