Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752277AbdH3DCr (ORCPT ); Tue, 29 Aug 2017 23:02:47 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:33783 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751995AbdH3DBV (ORCPT ); Tue, 29 Aug 2017 23:01:21 -0400 From: Philipp Rossak X-Google-Original-From: Philipp Rossak < embed3d@gmail.com > To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org Cc: Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Nanopi M1 Plus Date: Wed, 30 Aug 2017 05:01:06 +0200 Message-Id: <1504062070-13523-4-git-send-email-embed3d@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504062070-13523-1-git-send-email-embed3d@gmail.com> References: <1504062070-13523-1-git-send-email-embed3d@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1506 Lines: 68 From: Philipp Rossak The dwmac-sun8i hardware is present on the Nanopi M1 Plus. It uses an external PHY. Signed-off-by: Philipp Rossak --- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index ece275b..b9c6c27 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -45,6 +45,20 @@ / { model = "FriendlyArm NanoPi M1 Plus"; compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; }; &ehci1 { @@ -55,12 +69,30 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &ohci1 { status = "okay"; }; -- 2.7.4