Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751480AbdH3WAK (ORCPT ); Wed, 30 Aug 2017 18:00:10 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:34934 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751317AbdH3WAJ (ORCPT ); Wed, 30 Aug 2017 18:00:09 -0400 From: Stafford Horne To: LKML Cc: Openrisc , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Date: Thu, 31 Aug 2017 06:58:33 +0900 Message-Id: <65f12040f262906af8a599a85090f8482ef553cb.1504129273.git.shorne@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 615 Lines: 25 While working on SMP for OpenRISC I found this is needed for qrwlocks to work correctly. OpenRISC is big endian so this should have been here already. Signed-off-by: Stafford Horne --- arch/openrisc/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index ba8ae92ec5fb..8ddfc92ab813 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -29,6 +29,9 @@ config OPENRISC select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 select NO_BOOTMEM +config CPU_BIG_ENDIAN + def_bool y + config MMU def_bool y -- 2.13.5