Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750964AbdHaHrJ (ORCPT ); Thu, 31 Aug 2017 03:47:09 -0400 Received: from merlin.infradead.org ([205.233.59.134]:36004 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750884AbdHaHrI (ORCPT ); Thu, 31 Aug 2017 03:47:08 -0400 Date: Thu, 31 Aug 2017 09:46:54 +0200 From: Peter Zijlstra To: Stafford Horne Cc: LKML , Openrisc , Jonas Bonn , Stefan Kristiansson Subject: Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Message-ID: <20170831074654.aebcc7wvfbv7ebrw@hirez.programming.kicks-ass.net> References: <1a5c872fdf79d00c84ccd5ba3a5e02d02c1039c6.1504129273.git.shorne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1a5c872fdf79d00c84ccd5ba3a5e02d02c1039c6.1504129273.git.shorne@gmail.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 495 Lines: 10 On Thu, Aug 31, 2017 at 06:58:34AM +0900, Stafford Horne wrote: > OpenRISC only supports hardware instructions that perform 4 byte atomic > operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte > implementations are needed. To do this we leverage the 4 byte atomic > operations and shift/mask the 1 and 2 byte areas as needed. > > This heavily borrows ideas and routines from sh and mips, which do > something similar. Is there value in lifting them into something common?