Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751392AbdHaJBr (ORCPT ); Thu, 31 Aug 2017 05:01:47 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:38810 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750882AbdHaJB2 (ORCPT ); Thu, 31 Aug 2017 05:01:28 -0400 Date: Thu, 31 Aug 2017 18:01:25 +0900 From: Stafford Horne To: Peter Zijlstra Cc: LKML , Openrisc , Jonas Bonn , Stefan Kristiansson Subject: Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Message-ID: <20170831090125.GB2609@lianli.shorne-pla.net> References: <1a5c872fdf79d00c84ccd5ba3a5e02d02c1039c6.1504129273.git.shorne@gmail.com> <20170831074654.aebcc7wvfbv7ebrw@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170831074654.aebcc7wvfbv7ebrw@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.8.3 (2017-05-23) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 725 Lines: 16 On Thu, Aug 31, 2017 at 09:46:54AM +0200, Peter Zijlstra wrote: > On Thu, Aug 31, 2017 at 06:58:34AM +0900, Stafford Horne wrote: > > OpenRISC only supports hardware instructions that perform 4 byte atomic > > operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte > > implementations are needed. To do this we leverage the 4 byte atomic > > operations and shift/mask the 1 and 2 byte areas as needed. > > > > This heavily borrows ideas and routines from sh and mips, which do > > something similar. > > Is there value in lifting them into something common? Actually, I was planning on that as a followup patch series. Also, the timer sync patch [13/13] could me made common which is on my todo list.