Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751276AbdIACQq (ORCPT ); Thu, 31 Aug 2017 22:16:46 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:34814 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751009AbdIACQn (ORCPT ); Thu, 31 Aug 2017 22:16:43 -0400 X-Google-Smtp-Source: ADKCNb6pzZX4rAqQJW9JUuHIzr8EWyNGlCTJsmu/xKzNaA4Gw6JbXulpGG3MfVTNCgkpu2C+jQEoyw== Date: Fri, 1 Sep 2017 10:16:33 +0800 From: Leo Yan To: Stephen Boyd Cc: Wei Xu , Rob Herring , Mark Rutland , Michael Turquette , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Dmitry Shmidt , Guodong Xu , Haojian Zhuang Subject: Re: [PATCH 1/2] clk: hi6220: change watchdog clock source Message-ID: <20170901021633.GC516@leoy-ThinkPad-T440> References: <1503993518-24428-1-git-send-email-leo.yan@linaro.org> <20170901013240.GM21656@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170901013240.GM21656@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 665 Lines: 19 On Thu, Aug 31, 2017 at 06:32:40PM -0700, Stephen Boyd wrote: > On 08/29, Leo Yan wrote: > > The old code uses tcxo (19.2MHz) as watchdog clock but actually the > > watchdog uses 32K clock, as result the watchdog timeout cannot be set > > correctly and delay long time to reset SoC. > > > > So this patch is to use 'ref32k' as clock source for watchdog. > > > > Fixes: 72ea48610d43 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC") > > Signed-off-by: Leo Yan > > --- > > Applied to clk-next Thanks, Stephen. > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project