Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751849AbdIAH5F (ORCPT ); Fri, 1 Sep 2017 03:57:05 -0400 Received: from mail-io0-f196.google.com ([209.85.223.196]:35880 "EHLO mail-io0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751673AbdIAH4g (ORCPT ); Fri, 1 Sep 2017 03:56:36 -0400 X-Google-Smtp-Source: ADKCNb56bi8/jz14kdHl5FHq7g/4Ry1oak0Dkp629PwFI5Sffb2YnMe68fsXISx4e8ST0GFe2Tmkxw== From: Bin Meng To: Mika Westerberg , Cyrille Pitchen , Marek Vasut , Boris Brezillon , Brian Norris , Richard Weinberger , David Woodhouse , linux-mtd , linux-kernel Cc: Stefan Roese Subject: [PATCH 09/10] spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi' Date: Fri, 1 Sep 2017 01:00:40 -0700 Message-Id: <1504252841-2445-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1504252841-2445-1-git-send-email-bmeng.cn@gmail.com> References: <1504252841-2445-1-git-send-email-bmeng.cn@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2798 Lines: 87 The ispi->swseq is used for register access. Let's rename it to swseq_reg to better describe its usage. Signed-off-by: Bin Meng --- drivers/mtd/spi-nor/intel-spi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c index 91ceef7..5e7a389 100644 --- a/drivers/mtd/spi-nor/intel-spi.c +++ b/drivers/mtd/spi-nor/intel-spi.c @@ -126,7 +126,7 @@ * @pr_num: Maximum number of protected range registers * @writeable: Is the chip writeable * @locked: Is SPI setting locked - * @swseq: Use SW sequencer in register reads/writes + * @swseq_reg: Use SW sequencer in register reads/writes * @erase_64k: 64k erase supported * @opcodes: Opcodes which are supported. This are programmed by BIOS * before it locks down the controller. @@ -143,7 +143,7 @@ struct intel_spi { size_t pr_num; bool writeable; bool locked; - bool swseq; + bool swseq_reg; bool erase_64k; u8 opcodes[8]; u8 preopcodes[2]; @@ -224,7 +224,7 @@ static void intel_spi_dump_regs(struct intel_spi *ispi) } dev_dbg(ispi->dev, "Using %cW sequencer for register access\n", - ispi->swseq ? 'S' : 'H'); + ispi->swseq_reg ? 'S' : 'H'); } /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */ @@ -297,7 +297,7 @@ static int intel_spi_init(struct intel_spi *ispi) ispi->pregs = ispi->base + BYT_PR; ispi->nregions = BYT_FREG_NUM; ispi->pr_num = BYT_PR_NUM; - ispi->swseq = true; + ispi->swseq_reg = true; if (writeable) { /* Disable write protection */ @@ -318,7 +318,7 @@ static int intel_spi_init(struct intel_spi *ispi) ispi->pregs = ispi->base + LPT_PR; ispi->nregions = LPT_FREG_NUM; ispi->pr_num = LPT_PR_NUM; - ispi->swseq = true; + ispi->swseq_reg = true; break; case INTEL_SPI_BXT: @@ -343,7 +343,7 @@ static int intel_spi_init(struct intel_spi *ispi) * sequencer. All other operations are supposed to be carried out * using software sequencer. */ - if (ispi->swseq) { + if (ispi->swseq_reg) { /* Disable #SMI generation from SW sequencer */ val = readl(ispi->sregs + SSFSTS_CTL); val &= ~SSFSTS_CTL_FSMIE; @@ -493,7 +493,7 @@ static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) /* Address of the first chip */ writel(0, ispi->base + FADDR); - if (ispi->swseq) + if (ispi->swseq_reg) ret = intel_spi_sw_cycle(ispi, opcode, len, OPTYPE_READ_NO_ADDR); else @@ -529,7 +529,7 @@ static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) if (ret) return ret; - if (ispi->swseq) + if (ispi->swseq_reg) return intel_spi_sw_cycle(ispi, opcode, len, OPTYPE_WRITE_NO_ADDR); return intel_spi_hw_cycle(ispi, opcode, len); -- 2.9.2