Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751791AbdIAJAA (ORCPT ); Fri, 1 Sep 2017 05:00:00 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:36267 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751660AbdIAI7x (ORCPT ); Fri, 1 Sep 2017 04:59:53 -0400 Date: Fri, 1 Sep 2017 10:59:39 +0200 (CEST) From: Thomas Gleixner To: Ingo Molnar cc: Andrei Vagin , tip-bot for Jacob Shin , Cyrill Gorcunov , linux-tip-commits@vger.kernel.org, luto@kernel.org, peterz@infradead.org, rostedt@goodmis.org, linux-kernel@vger.kernel.org, hpa@zytor.com, brgerst@gmail.com, jpoimboe@redhat.com, bp@alien8.de, torvalds@linux-foundation.org, dvlasenk@redhat.com Subject: Re: [PATCH] x86/idt: Fix the X86_TRAP_BP gate In-Reply-To: <20170901082630.xvyi5bwk6etmppqc@gmail.com> Message-ID: References: <20170901062815.GA349@outlook.office365.com> <20170901082630.xvyi5bwk6etmppqc@gmail.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1842 Lines: 50 On Fri, 1 Sep 2017, Ingo Molnar wrote: > Subject: x86/idt: Fix the X86_TRAP_BP gate > From: Ingo Molnar > > Andrei Vagin reported a CRIU regression and bisected it back to: > > 90f6225fba0c ("x86/idt: Move IST stack based traps to table init") > > This table init conversion loses the system-gate property of X86_TRAP_BP > and erroneously moves it from DPL3 to DPL0. Duh, yes. Thanks for spotting it. > Fix it. > > Reported-by: Andrei Vagin > Cc: Linus Torvalds > Cc: Peter Zijlstra > Cc: Thomas Gleixner > Signed-off-by: Ingo Molnar > --- > arch/x86/kernel/idt.c | 6 +++++- > arch/x86/kernel/idt.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > Index: tip/arch/x86/kernel/idt.c > =================================================================== > --- tip.orig/arch/x86/kernel/idt.c > +++ tip/arch/x86/kernel/idt.c > @@ -44,6 +44,10 @@ struct idt_data { > #define ISTG(_vector, _addr, _ist) \ > G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS) > > +/* System interrupt gate with interrupt stack */ > +#define SISTG(_vector, _addr, _ist) \ > + G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS) > + > /* Task gate */ > #define TSKG(_vector, _gdt) \ > G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3) > @@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _ > static const __initdata struct idt_data ist_idts[] = { > ISTG(X86_TRAP_DB, debug, DEBUG_STACK), > ISTG(X86_TRAP_NMI, nmi, NMI_STACK), > - ISTG(X86_TRAP_BP, int3, DEBUG_STACK), > + SISTG(X86_TRAP_BP, int3, DEBUG_STACK), > ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK), > #ifdef CONFIG_X86_MCE > ISTG(X86_TRAP_MC, &machine_check, MCE_STACK), >