Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752779AbdIAW4r (ORCPT ); Fri, 1 Sep 2017 18:56:47 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:52426 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752563AbdIAWzR (ORCPT ); Fri, 1 Sep 2017 18:55:17 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E2476609F2 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 1 Sep 2017 15:55:14 -0700 From: Stephen Boyd To: Quentin Schulz Cc: mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, lgirdwood@gmail.com, broonie@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@free-electrons.com, linux@armlinux.org.uk, boris.brezillon@free-electrons.com, perex@perex.cz, tiwai@suse.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-arm-kernel@lists.infradead.org, cyrille.pitchen@wedev4u.fr, thomas.petazzoni@free-electrons.com, Nicolas Ferre Subject: Re: [PATCH v5 3/7] clk: at91: add audio pll clock drivers Message-ID: <20170901225514.GE21656@codeaurora.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 918 Lines: 23 On 08/10, Quentin Schulz wrote: > This new clock driver set allows to have a fractional divided clock that > would generate a precise clock particularly suitable for audio > applications. > > The main audio pll clock has two children clocks: one that is connected > to the PMC, the other that can directly drive a pad. As these two routes > have different enable bits and different dividers and divider formulas, > they are handled by two different drivers. Each of them could modify the > rate of the main audio pll parent. > > The main audio pll clock can output 620MHz to 700MHz. > > Signed-off-by: Nicolas Ferre > Signed-off-by: Quentin Schulz > Acked-by: Boris Brezillon > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project