Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753271AbdIDHGe (ORCPT ); Mon, 4 Sep 2017 03:06:34 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:33655 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752536AbdIDHGc (ORCPT ); Mon, 4 Sep 2017 03:06:32 -0400 Date: Mon, 4 Sep 2017 09:06:20 +0200 From: Maxime Ripard To: =?iso-8859-1?Q?Andr=E9?= Przywara Cc: Stefan =?iso-8859-1?Q?Br=FCns?= , linux-sunxi@googlegroups.com, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , Rob Herring , Code Kipper Subject: Re: [PATCH 01/10] dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3 Message-ID: <20170904070620.3lpkmq6nt2qrgwah@flea> References: <20170903224100.17893-1-stefan.bruens@rwth-aachen.de> <20170903224100.17893-2-stefan.bruens@rwth-aachen.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="iatbwsmpe4tb2w4b" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170714 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2544 Lines: 71 --iatbwsmpe4tb2w4b Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 04, 2017 at 12:23:09AM +0100, Andr=E9 Przywara wrote: > On 03/09/17 23:40, Stefan Br=FCns wrote: > > The H83T uses a compatible string different from the A23, but requires >=20 > A83T >=20 > > the same clock autogating register setting. > >=20 > > The H3 also requires setting the clock autogating register, but has > > the register at a different offset. > >=20 > > Some currently available SoCs not yet supported by the sun6i-dma driver > > will require new compatible strings. These SoCs either follow the A23 > > register model (e.g. V3s) or the H3 register model (A64, R40), so a new > > variable is added to the config struct to group SoCs with common regist= er > > models. >=20 > As mentioned in that other mail, using the actual properties as names > here instead of grouping them to rather arbitrary groups seems more > useful and future-proof to me and should be easier to read. > In this case this should simplify this patch: > sun8i_a23_dma_cfg =3D { > .nr_max_channels =3D 8, > .nr_max_requests =3D 24, > .nr_max_vchans =3D 37, > + .auto_clock_gate =3D 0x20, > ... > - if (of_device_is_compatible(pdev->dev.of_node, > - "allwinner,sun8i-a23-dma")) > - writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE); > + if (sdc->cfg->auto_clock_gate) > + writel(SUN8I_DMA_GATE_ENABLE, > + sdc->base + sdc->cfg->auto_clock_gate); I agree. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --iatbwsmpe4tb2w4b Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBAgAGBQJZrPtrAAoJEBx+YmzsjxAgQuUP/3JYzWfaEoi3T11Pz3hu0Kcn 4EKA+vrCUxXR5kWRZZ8Lx71YKfCRiMVLLhEumyE/nXkgtKo6P0v3Cf2S42mcDq3j xoffwRPx84Yp7EByAWAxTGI3aLprSQsO0dyUHW6VJBs/Fdid+HjXMY+MOAnAPjXE wrIvzwEDMINHhgjkwmuRDrANue/RSci3ynQBJNyZ27RVqVZ/znMlpZM0uywDRrjJ DbmEyE0dEZ/AG3SfyNbEIgNcqfmXraOVvF4/0LczKvlHrmkIxQMQRtQn7S5MJ4MA BIOMz3P8sFUgqjXkIt0eO2Q44su3g7tpUsR0GjIVBLbC2aNK/QXqnL4Tk3Bj9B78 t9UPCRSLN5JgPnBk1WScNfrD3eAJsTXBolt1hvIqWTRNMTdrYNamd8u+zAe2b1bq kEf7Un02WOMXjrI1cKCrGWMit0hNsI5yh/auZ+NdcNVCxbwyvEgkczpTz2cKRn9y UG3sSB/LQexAd8VSbeYnn6JeWUgo80ps+cTouaqiioSmp2GZQeRQUhSd91KH82xQ ApUMBZ2Lr/ezBMmm+SG+5cjWY/7Gg98xDow6Ch0l83uQkBY0S0Ma3Zjpa+dFrw6g ttAxdrd+LsNcLXKRXlFEeHB+JXjPc+cDMljDXtuvy/8kpuCuut4DLOIPHJMQ1Bsp CPO7YkPEaShiPU2kbqkm =pWEi -----END PGP SIGNATURE----- --iatbwsmpe4tb2w4b--