Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753577AbdIDLYz (ORCPT ); Mon, 4 Sep 2017 07:24:55 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5534 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753443AbdIDLYx (ORCPT ); Mon, 4 Sep 2017 07:24:53 -0400 Subject: Re: [PATCH v6 1/7] arm64: cpufeature: Detect CPU RAS Extentions To: James Morse References: <1503916701-13516-1-git-send-email-gengdongjiu@huawei.com> <1503916701-13516-2-git-send-email-gengdongjiu@huawei.com> <59A84AF5.3000104@arm.com> CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , From: gengdongjiu Message-ID: <4271bbe8-fc99-c213-55b2-2171985a81dd@huawei.com> Date: Mon, 4 Sep 2017 19:20:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <59A84AF5.3000104@arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.68.147] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59AD3711.0015,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: cc1c643cd25ba5ced3bf237e8455ef81 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2017 Lines: 65 James, On 2017/9/1 1:44, James Morse wrote: > Hi Dongjiu Geng, > > On 28/08/17 11:38, Dongjiu Geng wrote: >> From: Xie XiuQi >> >> ARM's v8.2 Extentions add support for Reliability, Availability and >> Serviceability (RAS). On CPUs with these extensions system software >> can use additional barriers to isolate errors and determine if faults >> are pending. >> >> Add cpufeature detection and a barrier in the context-switch code. >> There is no need to use alternatives for this as CPUs that don't >> support this feature will treat the instruction as a nop. >> >> Platform level RAS support may require additional firmware support. >> >> Signed-off-by: Xie XiuQi >> [Rebased, added esb and config option, reworded commit message] >> Signed-off-by: James Morse > > Nit: when re-posting patches from the list you need to add your signed-off-by. > See Documentation/process/submitting-patches.rst 'Developer's Certificate of > Origin 1.1' Ok, thanks for the your pointing out. > > This goes for your patch 2 as well. > > >> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c >> index c845c8c04d95..7a17b4a1bd9e 100644 >> --- a/arch/arm64/kernel/process.c >> +++ b/arch/arm64/kernel/process.c >> @@ -370,6 +370,9 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, >> */ >> dsb(ish); >> >> + /* Deliver any pending SError from prev */ >> + esb(); >> + > > This patch was sitting on top of the SError rework. As the cover-letter > describes that was all there to make sure SError is unmasked when we execute > this esb(). Without it any pending SError will be deferred, its ESR is written > to DISR_EL1, which this patch doesn't check. > > On its own, this patch is actively harmful to systems that don't have > firmware-first handling. > > We probably need to produce a combined series... OK, thanks for your reminder and detailed explanation. > > > Thanks, > > James > > > . >