Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753664AbdIDNBv (ORCPT ); Mon, 4 Sep 2017 09:01:51 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:42096 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753504AbdIDNBu (ORCPT ); Mon, 4 Sep 2017 09:01:50 -0400 Date: Mon, 4 Sep 2017 15:01:46 +0200 (CEST) From: Thomas Gleixner To: "Kirill A. Shutemov" cc: Ingo Molnar , Linus Torvalds , linux-kernel@vger.kernel.org, "H. Peter Anvin" , Peter Zijlstra , Andrew Morton , Andy Lutomirski , Borislav Petkov Subject: Re: [GIT PULL] x86/mm changes for v4.14: PCID support, 5-level paging support, Secure Memory Encryption support In-Reply-To: <20170904122358.uscplql7tzrnimp4@node.shutemov.name> Message-ID: References: <20170904093158.k6pg3ytcbotjlhv5@gmail.com> <20170904122358.uscplql7tzrnimp4@node.shutemov.name> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 707 Lines: 17 On Mon, 4 Sep 2017, Kirill A. Shutemov wrote: > On Mon, Sep 04, 2017 at 11:31:58AM +0200, Ingo Molnar wrote: > > The main changes in this cycle are support for three new, complex hardware > > features of x86 CPUs: > > > > - Add 5-level paging support, which is a new hardware feature on upcoming Intel > > CPUs allowing up to 128 PB of virtual address space and 4 PB of physical RAM > > space - a 256-fold increase over the old limits. > > Minor nitpick: I don't see where "256-fold" comes from. > > Virtual address space increased from 256 TB to 128 PB -- 512 times. > Physical: 64 TB -> 4 PB -- 64 times. See arch/x86/kernel/tsc.c: -johnstul@us.ibm.com "math is hard, lets go shopping!"