Date: Mon, 4 Sep 2017 15:54:15 +0200
From: Ingo Molnar <mingo@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: "Kirill A. Shutemov" <kirill@shutemov.name>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        linux-kernel@vger.kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
        Peter Zijlstra <a.p.zijlstra@chello.nl>,
        Andrew Morton <akpm@linux-foundation.org>,
        Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@alien8.de>
Subject: Re: [GIT PULL] x86/mm changes for v4.14: PCID support, 5-level
 paging support, Secure Memory Encryption support
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* Thomas Gleixner <tglx@linutronix.de> wrote:

> On Mon, 4 Sep 2017, Kirill A. Shutemov wrote:
> > On Mon, Sep 04, 2017 at 11:31:58AM +0200, Ingo Molnar wrote:
> > > The main changes in this cycle are support for three new, complex hardware 
> > > features of x86 CPUs:
> > > 
> > >  - Add 5-level paging support, which is a new hardware feature on upcoming Intel
> > >    CPUs allowing up to 128 PB of virtual address space and 4 PB of physical RAM 
> > >    space - a 256-fold increase over the old limits.
> > 
> > Minor nitpick: I don't see where "256-fold" comes from.
> > 
> > Virtual address space increased from 256 TB to 128 PB -- 512 times.
> > Physical: 64 TB -> 4 PB -- 64 times.
> 
> See arch/x86/kernel/tsc.c:
> 
>     -johnstul@us.ibm.com "math is hard, lets go shopping!"

Yeah, I mis-remembered the increase in number of bits, should have double checked ...

/me goes shopping

Thanks,

	Ingo