Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753021AbdIGBoJ (ORCPT ); Wed, 6 Sep 2017 21:44:09 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:5989 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751369AbdIGBoG (ORCPT ); Wed, 6 Sep 2017 21:44:06 -0400 Subject: Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3 To: Jean-Philippe Brucker , Yisheng Xie References: <1504167642-14922-1-git-send-email-xieyisheng1@huawei.com> <95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com> <2874a1f3-22f1-20d4-4009-50add127a10f@arm.com> CC: , , , , , , , , , , , , , , , , , , , From: Bob Liu Message-ID: <1d358989-48bb-ccde-d7d9-36e004bc2d78@huawei.com> Date: Thu, 7 Sep 2017 09:41:42 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <2874a1f3-22f1-20d4-4009-50add127a10f@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.142.83.150] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59B0A44A.0112,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1fbf0095867358040b476e1df2032556 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4075 Lines: 92 On 2017/9/6 17:57, Jean-Philippe Brucker wrote: > On 06/09/17 02:02, Bob Liu wrote: >> On 2017/9/5 20:56, Jean-Philippe Brucker wrote: >>> On 31/08/17 09:20, Yisheng Xie wrote: >>>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3: >>>> https://www.spinics.net/lists/arm-kernel/msg565155.html >>>> >>>> But for some platform devices(aka on-chip integrated devices), there is also >>>> SVM requirement, which works based on the SMMU stall mode. >>>> Jean-Philippe has prepared a prototype patchset to support it: >>>> git://linux-arm.org/linux-jpb.git svm/stall >>> >>> Only meant for testing at that point, and unfit even for an RFC. >>> >> >> Sorry for the misunderstanding. >> The PRI mode patches is in RFC even no hardware for testing, so I thought it's fine for "Stall mode" patches sent as RFC. >> We have tested the Stall mode on our platform. >> Anyway, I should confirm with you in advance. >> >> Btw, Would you consider the "stall mode" upstream at first? Since there is no hardware for testing the PRI mode. >> (We can provide you the hardware which support SMMU stall mode if necessary.) > > Yes. What's blocking the ATS, PRI and PASID patches at the moment is the > lack of endpoints for testing. There has been lots of discussion on the > API side since my first RFC and I'd like to resubmit the API changes soon. > It is the same API for ATS+PRI+PASID and SSID+Stall, so the backend > doesn't matter. > Indeed! > I'm considering upstreaming SSID+Stall first if it can be tested on > hardware (having direct access to it would certainly speed things up). Glad to hear that. > This would require some work in moving the PCI bits at the end of the > series. I can reserve some time in the coming months to do it, but I need > to know what to focus on. Are you able to test SSID as well? > Yes, but the difficulty is our devices are on-chip integrated hardware accelerators which requires complicate driver. You may need much time to understand the driver. That's the same case as intel/amd SVM, the current user is their GPU :-( Btw, what kind of device/method do you think is ideal for testing arm-SVM? >>>> We tested this patchset with some fixes on a on-chip integrated device. The >>>> basic function is ok, so I just send them out for review, although this >>>> patchset heavily depends on the former patchset (PCIe SVM support for ARM >>>> SMMUv3), which is still under discussion. >>>> >>>> Patch Overview: >>>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits >>>> *4 is to realise the SVM function for platform device >>>> *5 is fix a bug when test SVM function while SMMU donnot support this feature >>>> *6 avoid ILLEGAL setting of STE and CD entry about stall >>>> >>>> Acctually here, I also have a question about SVM on SMMUv3: >>>> >>>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device, >>>> it will register a mmu_notify. Therefore, when a page range is invalid, we can >>>> send TLBI or ATC invalid without BTM? >>> >>> We could, but the end goal for SVM is to perfectly mirror the CPU page >>> tables. So for platform SVM we would like to get rid of MMU notifiers >>> entirely. >>> >>>> 2. According to ACPI IORT spec, named component specific data has a node flags field >>>> whoes bit0 is for Stall support. However, it do not have any field for pasid bit. >>>> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for >>>> a single platform device which should be enough, because SMMU only support 20 bit pasid >>>> >> >> Any comment on this? >> The ACPI IORT spec may need be updated? > > I suppose that the Named Component Node could be used for SSID and stall > capability bits. Can't the ACPI namespace entries be extended to host > these capabilities in a more generic way? Platforms with different IOMMUs > might also need this information some day. > Hmm, that would be better. But in anyway, it depends on the ACPI IORT Spec would be extended in next version. -- Thanks, Bob Liu