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To: root@chaos.analogic.com
Cc: kernel@kvack.org, "Dr. David Gilbert" <dg@px.uk.com>,
        linux-kernel@vger.kernel.org
Subject: Re: Dual XEON - >>SLOW<< on SMP
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Reply-To: drepper@cygnus.com (Ulrich Drepper)
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From: Ulrich Drepper <drepper@redhat.com>
Date: 02 Nov 2000 10:09:36 -0800
In-Reply-To: "Richard B. Johnson"'s message of "Thu, 2 Nov 2000 09:02:38 -0500 (EST)"
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"Richard B. Johnson" <root@chaos.analogic.com> writes:

> Yes. Look at the NMI count. Looks like every access produces a
> NMI.

I'm seeing this as well, but only with PIII Xeon systems, not PII
Xeon.  Every single timer interrupt on any CPU is accompanied by a NMI
and LOC increment on every CPU.

           CPU0       CPU1       
  0:     146727     153389    IO-APIC-edge  timer
[...]
NMI:     300035     300035 
LOC:     300028     300028 


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