Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756017AbdIHIMM (ORCPT ); Fri, 8 Sep 2017 04:12:12 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:37471 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754695AbdIHIKz (ORCPT ); Fri, 8 Sep 2017 04:10:55 -0400 X-Google-Smtp-Source: ADKCNb60yaSb6bdG9q0Sx9lYWBybnMoxPKmuzrdf0ZZ4j1YYFayCMeXYxpjRg4HZcqBalPqUqWInGg== From: Jan Glauber To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, Alex Williamson , linux-kernel@vger.kernel.org, david.daney@cavium.com, Jon Masters , Robert Richter , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Jan Glauber Subject: [PATCH v4 2/3] PCI: Avoid bus reset for Cavium cn8xxx root ports Date: Fri, 8 Sep 2017 10:10:32 +0200 Message-Id: <20170908081033.3025-3-jglauber@cavium.com> X-Mailer: git-send-email 2.9.0.rc0.21.g7777322 In-Reply-To: <20170908081033.3025-1-jglauber@cavium.com> References: <20170908081033.3025-1-jglauber@cavium.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1251 Lines: 34 From: David Daney Root ports of cn8xxx do not function after bus reset when used with some e1000e and LSI HBA devices. Add a quirk to prevent bus reset on these root ports. Signed-off-by: David Daney [jglauber@cavium.com: fixed typo and whitespaces] Signed-off-by: Jan Glauber --- drivers/pci/quirks.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 140760403f36..2e4e7b6d1a79 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3364,6 +3364,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); +/* + * Root port on some Cavium CN8xxx chips do not successfully complete + * a bus reset when used with certain types of child devices. Config + * space access to the child may quit responding. Flag the root port + * as not supporting bus reset. + */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); + static void quirk_no_pm_reset(struct pci_dev *dev) { /* -- 2.9.0.rc0.21.g7777322