Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756786AbdIHS4p (ORCPT ); Fri, 8 Sep 2017 14:56:45 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:47304 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756210AbdIHS4m (ORCPT ); Fri, 8 Sep 2017 14:56:42 -0400 Subject: Re: [PATCH] ARC: HSDK: DTS: Temporary fix of sdio ciu frequency To: Eugeniy Paltsev , "linux-snps-arc@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , "Alexey Brodkin" , Rob Herring , "devicetree@vger.kernel.org" References: <20170908184233.1779-1-Eugeniy.Paltsev@synopsys.com> From: Vineet Gupta Message-ID: <3bed30b7-6efe-e3d4-a65a-b6816e87c45e@synopsys.com> Date: Fri, 8 Sep 2017 11:56:37 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170908184233.1779-1-Eugeniy.Paltsev@synopsys.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.10.161.108] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1544 Lines: 46 On 09/08/2017 11:42 AM, Eugeniy Paltsev wrote: > DW sdio controller has external ciu clock devider controlled via > register in SDIO IP. Due to its unexpected default value > (it should devide by 1 but it devides by 8) > SDIO IP uses wrong ciu clock and works unstable (see STAR 9001204800) > > So add temporary fix and change clock frequency from 100000000 > to 12500000 Hz until we fix dw sdio driver itself. > > Signed-off-by: Eugeniy Paltsev Added. Consider it bike shedding, but for next time, please bracket the platform patches as ARC: [plat-xxx] abra ka dabra .... -Vineet > --- > arch/arc/boot/dts/hsdk.dts | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts > index 8412669..b922f3f 100644 > --- a/arch/arc/boot/dts/hsdk.dts > +++ b/arch/arc/boot/dts/hsdk.dts > @@ -127,7 +127,17 @@ > > mmcclk_ciu: mmcclk-ciu { > compatible = "fixed-clock"; > - clock-frequency = <100000000>; > + /* > + * DW sdio controller has external ciu clock divider > + * controlled via register in SDIO IP. Due to its > + * unexpected default value (it should devide by 1 > + * but it devides by 8) SDIO IP uses wrong clock and > + * works unstable (see STAR 9001204800) > + * So add temporary fix and change clock frequency > + * from 100000000 to 12500000 Hz until we fix dw sdio > + * driver itself. > + */ > + clock-frequency = <12500000>; > #clock-cells = <0>; > }; >