Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932739AbdIHVfB (ORCPT ); Fri, 8 Sep 2017 17:35:01 -0400 Received: from mga14.intel.com ([192.55.52.115]:45303 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932599AbdIHVfA (ORCPT ); Fri, 8 Sep 2017 17:35:00 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,363,1500966000"; d="scan'208";a="149827836" From: kan.liang@intel.com To: tglx@linutronix.de, peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org Cc: harry.pan@intel.com, srinivas.pandruvada@linux.intel.com, piotr.luc@intel.com, ak@linux.intel.com, Kan Liang Subject: [PATCH 2/3] perf/x86/msr: add missing CPU IDs Date: Fri, 8 Sep 2017 17:34:48 -0400 Message-Id: <20170908213449.6224-2-kan.liang@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170908213449.6224-1-kan.liang@intel.com> References: <20170908213449.6224-1-kan.liang@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 764 Lines: 30 From: Kan Liang Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well. Signed-off-by: Kan Liang --- arch/x86/events/msr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 4bb3ec6..0672367 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -63,6 +63,14 @@ static bool test_intel(int idx) case INTEL_FAM6_ATOM_SILVERMONT1: case INTEL_FAM6_ATOM_SILVERMONT2: case INTEL_FAM6_ATOM_AIRMONT: + + case INTEL_FAM6_ATOM_GOLDMONT: + case INTEL_FAM6_ATOM_DENVERTON: + + case INTEL_FAM6_ATOM_GEMINI_LAKE: + + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: if (idx == PERF_MSR_SMI) return true; break; -- 2.9.4