Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752668AbdIISOs (ORCPT ); Sat, 9 Sep 2017 14:14:48 -0400 Received: from ud10.udmedia.de ([194.117.254.50]:54720 "EHLO mail.ud10.udmedia.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751261AbdIISOr (ORCPT ); Sat, 9 Sep 2017 14:14:47 -0400 Date: Sat, 9 Sep 2017 20:14:45 +0200 From: Markus Trippelsdorf To: Borislav Petkov Cc: Andy Lutomirski , Ingo Molnar , Thomas Gleixner , Peter Zijlstra , LKML , Ingo Molnar , Tom Lendacky Subject: Re: Current mainline git (24e700e291d52bd2) hangs when building e.g. perf Message-ID: <20170909181445.GA281@x4> References: <20170909133745.GA289@x4> <20170909133954.GB289@x4> <20170909140700.bp7jonmp7etlb7ov@pd.tnic> <20170909142014.GC289@x4> <20170909143335.ja2iwjsbeyfxz4ez@pd.tnic> <20170909144350.GA290@x4> <20170909163225.GA290@x4> <20170909170537.6xmxtzwripplhhwi@pd.tnic> <20170909172352.GA290@x4> <20170909173633.4ttfk7maooxkcwum@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170909173633.4ttfk7maooxkcwum@pd.tnic> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1115 Lines: 30 On 2017.09.09 at 19:36 +0200, Borislav Petkov wrote: > On Sat, Sep 09, 2017 at 07:23:52PM +0200, Markus Trippelsdorf wrote: > > Hmm, the output is exactly the same as before your patch. > > Bah, that patch doesn't account for the fact that we're rereading the > status field again in do_machine_check(). > > Ok, let's force MCi_ADDR out. Ontop: Thanks, will try it later. I think the issue gets fixed by: # wrmsr -a 0xc0010015 0x1000018 Setting bit 3 of the Hardware Configuration Register to 1. Quote for the docs: ?TlbCacheDis: cacheable memory disable. Read-write. 0=Enables performance optimization that assumes PML4, PDP, PDE, and PTE entries are in cacheable WB-DRAM; memory type checks may be bypassed, and addresses outside of WB-DRAM may result in undefined behavior or NB protocol errors. 1=Disables performance optimization and allows PML4, PDP, PDE and PTE entries to be in any memory type. Operating systems that maintain page tables in memory types other than WB- DRAM must set TlbCacheDis to insure proper operation.? I've been successfully compiling for over 15 minutes now. -- Markus