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Date: Thu, 2 Nov 2000 20:26:21 +0200
From: Matti Aarnio <matti.aarnio@zmailer.org>
To: linux-kernel@vger.kernel.org
Cc: kernel@kvack.org
Subject: Re: Dual XEON - >>SLOW<< on SMP
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In-Reply-To: <Pine.LNX.3.95.1001102090044.8621A-100000@chaos.analogic.com> <m3bsvy2qlb.fsf@otr.mynet.cygnus.com>
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In-Reply-To: <m3bsvy2qlb.fsf@otr.mynet.cygnus.com>; from drepper@redhat.com on Thu, Nov 02, 2000 at 10:09:36AM -0800
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On Thu, Nov 02, 2000 at 10:09:36AM -0800, Ulrich Drepper wrote:
> "Richard B. Johnson" <root@chaos.analogic.com> writes:
> > Yes. Look at the NMI count. Looks like every access produces a
> > NMI.
> 
> I'm seeing this as well, but only with PIII Xeon systems, not PII
> Xeon.  Every single timer interrupt on any CPU is accompanied by a NMI
> and LOC increment on every CPU.

	Same happens with PIII CopperMine too.
	I have Asus P2B-DS board and 1 GB RAM.

>            CPU0       CPU1       
>   0:     146727     153389    IO-APIC-edge  timer
> [...]
> NMI:     300035     300035 
> LOC:     300028     300028 

/Matti Aarnio
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