Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751357AbdIJGuF (ORCPT ); Sun, 10 Sep 2017 02:50:05 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:34359 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751193AbdIJGt7 (ORCPT ); Sun, 10 Sep 2017 02:49:59 -0400 X-Google-Smtp-Source: ADKCNb5scuWGqsnlhu/GWd/GqjnTPRXjBNniMow8pVhaNBuIqt+KUx4bKh7fLehbKJ0Dyo60DAAAaA== From: Stafford Horne To: LKML Cc: Openrisc , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true Date: Sun, 10 Sep 2017 15:49:14 +0900 Message-Id: <20170910064926.5874-3-shorne@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910064926.5874-1-shorne@gmail.com> References: <20170910064926.5874-1-shorne@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 615 Lines: 25 While working on SMP for OpenRISC I found this is needed for qrwlocks to work correctly. OpenRISC is big endian so this should have been here already. Signed-off-by: Stafford Horne --- arch/openrisc/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index ee34d94f7aa2..356dd67a86ea 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -29,6 +29,9 @@ config OPENRISC select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 select NO_BOOTMEM +config CPU_BIG_ENDIAN + def_bool y + config MMU def_bool y -- 2.13.5