DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 57F5C14792D
Message-ID: <1505092341.21121.34.camel@redhat.com>
Subject: Re: Current mainline git (24e700e291d52bd2) hangs when building
 e.g. perf
From: Rik van Riel <riel@redhat.com>
To: Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
        Markus Trippelsdorf <markus@trippelsdorf.de>,
        Ingo Molnar <mingo@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
        Peter Zijlstra <peterz@infradead.org>,
        LKML <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@redhat.com>,
        Tom Lendacky <thomas.lendacky@amd.com>
Date: Sun, 10 Sep 2017 21:12:21 -0400
In-Reply-To: <CALCETrXp=WVhMasO=xvNy556CoBgDqJx6xEfN3jdTJOJB4LFUg@mail.gmail.com>
References: <20170909143335.ja2iwjsbeyfxz4ez@pd.tnic>
         <20170909144350.GA290@x4> <20170909163225.GA290@x4>
         <20170909170537.6xmxtzwripplhhwi@pd.tnic> <20170909172352.GA290@x4>
         <20170909173633.4ttfk7maooxkcwum@pd.tnic> <20170909181445.GA281@x4>
         <CA+55aFwCSaY2qZdt9SC+hhXOz9V=z63=uzOYgWNxKJ5kgnXCbg@mail.gmail.com>
         <20170909182952.itqad4ryngjwrgqf@pd.tnic>
         <CA+55aFzxsKzuYKMCXQA+54GUhRzEMCtwYWdj+RTDv7LHUhVj4Q@mail.gmail.com>
         <20170909190948.xydyega7i2rjnlqt@pd.tnic>
         <CALCETrXp=WVhMasO=xvNy556CoBgDqJx6xEfN3jdTJOJB4LFUg@mail.gmail.com>
Organization: Red Hat, Inc
Content-Type: text/plain; charset="UTF-8"
Mime-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Content-Length: 1156
Lines: 28

On Sat, 2017-09-09 at 12:28 -0700, Andy Lutomirski wrote:
> -
> I propose the following fix.  If PCID is on, then, in
> enter_lazy_tlb(), we switch to init_mm with the no-flush flag set.
> (And we give init_mm its own dedicated ASID to keep it simple and
> fast
> -- no need to use the LRU ASID mapping to assign one
> dynamically.)  We
> clear the bit in mm_cpumask.  That is, we more or less just skip the
> whole lazy TLB optimization and rely on PCID CPUs having reasonably
> fast CR3 writes.  No extra IPIs.

Avoiding the IPIs is probably what matters the most, especially
on systems with deep C states, and virtual machines where the
host may be running something else, causing the IPI service time
to go through the roof for idle VCPUs.

> Also, sorry Rik, this means your old increased laziness optimization
> is dead in the water.  It will have exactly the same speculative load
> problem.

Doesn't a memory barrier solve that speculative load
problem?

The memory barrier could be added only to the path
that potentially skips reloading the TLB, under the
assumption that a memory barrier is cheaper than a
TLB reload (even with ASID).