Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751212AbdIKHZy (ORCPT ); Mon, 11 Sep 2017 03:25:54 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:34553 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750940AbdIKHZw (ORCPT ); Mon, 11 Sep 2017 03:25:52 -0400 X-Google-Smtp-Source: ADKCNb6SClx9KEod8PWcmCOPwmSpAb5bP/FzUGZoLaLXS5PelZN9PY5HXLazec25ScwBA8pRk/QO3A== Date: Mon, 11 Sep 2017 15:25:39 +0800 From: Dong Aisheng To: Dong Aisheng Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sboyd@codeaurora.org, mturquette@baylibre.com, shawnguo@kernel.org, Anson.Huang@nxp.com, ping.bai@nxp.com Subject: Re: [PATCH V2 00/10] clk: add imx7ulp clk support Message-ID: <20170911072539.GA19297@b29396-OptiPlex-7040> References: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3377 Lines: 76 Hi Stephen, On Thu, Jul 13, 2017 at 07:47:05PM +0800, Dong Aisheng wrote: > This patch series intends to add imx7ulp clk support. > > i.MX7ULP Clock functions are under joint control of the System > Clock Generation (SCG) modules, Peripheral Clock Control (PCC) > modules, and Core Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain > and A7 domain. Except for a few clock sources shared between two > domains, such as the System Oscillator clock, the Slow IRC (SIRC), > and and the Fast IRC clock (FIRCLK), clock sources and clock > management are separated and contained within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Note: this series only adds A7 clock domain support as M4 clock > domain will be handled by M4 seperately. > > Change Log: > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for possible > timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for > the left normal peripheral clocks registered by a platform driver. Would you please help review this new series when you're free? This has been pending for a long time. Regards Dong Aisheng > > Dong Aisheng (10): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: reparent orphans after critical clocks enabled > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver > > .../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++ > drivers/clk/clk-divider.c | 100 ++++++++- > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/clk.c | 39 ++-- > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c | 90 ++++++++ > drivers/clk/imx/clk-fixup-mux.c | 2 +- > drivers/clk/imx/clk-imx7ulp.c | 245 +++++++++++++++++++++ > drivers/clk/imx/clk-pfdv2.c | 207 +++++++++++++++++ > drivers/clk/imx/clk-pllv4.c | 188 ++++++++++++++++ > drivers/clk/imx/clk.c | 22 ++ > drivers/clk/imx/clk.h | 92 +++++++- > include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++ > include/linux/clk-provider.h | 17 ++ > 15 files changed, 1159 insertions(+), 31 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c > create mode 100644 drivers/clk/imx/clk-imx7ulp.c > create mode 100644 drivers/clk/imx/clk-pfdv2.c > create mode 100644 drivers/clk/imx/clk-pllv4.c > create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h > > -- > 2.7.4 >