Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751305AbdILEhf (ORCPT ); Tue, 12 Sep 2017 00:37:35 -0400 Received: from mail-yw0-f179.google.com ([209.85.161.179]:36061 "EHLO mail-yw0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751045AbdILEhe (ORCPT ); Tue, 12 Sep 2017 00:37:34 -0400 X-Google-Smtp-Source: AOwi7QBHNw9Xewupr1+9mu+vJ3qB/wJpoaZKv3HzzNprW8gMjN1ZgrUkhHN9LsAdQkf/odjLyXD2piiAqIgNVlgmLnk= MIME-Version: 1.0 In-Reply-To: <1616508443.22335.1504032937518.JavaMail.zimbra@efficios.com> References: <20170827213659.29210-1-mathieu.desnoyers@efficios.com> <1616508443.22335.1504032937518.JavaMail.zimbra@efficios.com> From: Max Filippov Date: Mon, 11 Sep 2017 21:37:33 -0700 Message-ID: Subject: Re: [PATCH] Fix: xtensa: add missing sync_core To: Mathieu Desnoyers Cc: "Paul E. McKenney" , linux-kernel , Peter Zijlstra , Chris Zankel , "linux-xtensa@linux-xtensa.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1687 Lines: 37 Hi Mathieu, On Tue, Aug 29, 2017 at 11:55 AM, Mathieu Desnoyers wrote: > ----- On Aug 28, 2017, at 1:12 PM, Max Filippov jcmvbkbc@gmail.com wrote: >> On Mon, Aug 28, 2017 at 12:36 AM, Mathieu Desnoyers >> wrote: >>> The membarrier system call now requires all architectures to implement >>> sync_core(). On Xtensa, it is provided by the EXTW instruction. >>> >>> [ Completely untested! Can someone on the xtensa side confirm whether >>> EXTW is the right way to serialize core execution and try it out ? ] >> >> Thanks for the patch. I'm currently travelling, I'll give it a try next week >> once I'm back at work. > > I think we may need to flush the icache to make it consistent with the dcache > too on xtensa, in addition to the EXTW. The goal here is to allow JIT engines > to reclaim and re-use memory after they discard dynamically generated code. > This is similar to what we'd need to do on arm32, where they have inconsistent > d/i-caches. my understanding is that to support JIT engines on xtensa we need to do icache/dcache synchronization, this procedure is covered in the ISYNC instruction description in the ISA book, it involves MEMW and ISYNC, but not EXTW. EXTW is meant to work as a CPU barrier that orders all externally visible CPU signals, which seems unnecessary. Interestingly, currently we don't have MEMW between dcache flush and icache invalidation, so I need to add it to be consistent with the documented procedure. Then I believe that sync_core implementation should invoke flush_dcache_all followed by MEMW followed by invalidate_icache_all. Does that sound right? -- Thanks. -- Max