Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751463AbdILSif (ORCPT ); Tue, 12 Sep 2017 14:38:35 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:57318 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751038AbdILSic (ORCPT ); Tue, 12 Sep 2017 14:38:32 -0400 Subject: Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency To: Eugeniy Paltsev , "linux-snps-arc@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , "Alexey Brodkin" , Rob Herring , "devicetree@vger.kernel.org" References: <20170912182045.20941-1-Eugeniy.Paltsev@synopsys.com> From: Vineet Gupta Message-ID: <4df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com> Date: Tue, 12 Sep 2017 11:38:23 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170912182045.20941-1-Eugeniy.Paltsev@synopsys.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.10.161.108] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1333 Lines: 37 On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote: > DW sdio controller has external ciu clock divider controlled > via register in SDIO IP. It divides sdio_ref_clk > (which comes from CGU) by 16 for default. So default mmcclk > clock (which comes to sdk_in) is 25000000 Hz. > > So fix wrong current value (50000000 Hz) to actual 25000000 Hz. Is this a preventive fix or there are known issues with what we have today. Is this triggered after addition of AXS clk driver ? > > Signed-off-by: Eugeniy Paltsev > --- > arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi > index 0ff7e07..7bdf581 100644 > --- a/arch/arc/boot/dts/axs10x_mb.dtsi > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi > @@ -44,7 +44,14 @@ > > mmcclk: mmcclk { > compatible = "fixed-clock"; > - clock-frequency = <50000000>; > + /* > + * DW sdio controller has external ciu clock divider > + * controlled via register in SDIO IP. It divides > + * sdio_ref_clk (which comes from CGU) by 16 for > + * default. So default mmcclk clock (which comes > + * to sdk_in) is 25000000 Hz. > + */ > + clock-frequency = <25000000>; > #clock-cells = <0>; > }; >