Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751635AbdIMCLZ (ORCPT ); Tue, 12 Sep 2017 22:11:25 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:46943 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751173AbdIMCLX (ORCPT ); Tue, 12 Sep 2017 22:11:23 -0400 X-Google-Smtp-Source: AOwi7QCiE1LaoR6oVoIE4rWVJXHTkrE2h/acy6Do+k+eOig1rovx9yNrg2nO1/3mmPIxaGXNCZsBtFOZXaq9hiaghBY= MIME-Version: 1.0 In-Reply-To: <1505151868.31322.98.camel@infinera.com> References: <1505122921-5534-1-git-send-email-bmeng.cn@gmail.com> <1505151868.31322.98.camel@infinera.com> From: Bin Meng Date: Wed, 13 Sep 2017 10:11:21 +0800 Message-ID: Subject: Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and enhancements To: Joakim Tjernlund Cc: "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "mika.westerberg@linux.intel.com" , "cyrille.pitchen@wedev4u.fr" , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "boris.brezillon@free-electrons.com" , "marek.vasut@gmail.com" , "richard@nod.at" , "sr@denx.de" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1324 Lines: 30 Hi Joakim, On Tue, Sep 12, 2017 at 1:44 AM, Joakim Tjernlund wrote: > On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote: >> This series does several bug fixes and clean ups against the intel-spi >> spi-nor driver, as well as enhancements to make the driver independent >> on the underlying BIOS/bootloader. >> >> At present the driver uses the HW sequencer for the read/write/erase on >> all supported platforms, read_reg/write_reg for BXT, and the SW sequencer >> for read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW >> sequencer relies on some programmed register settings and hence creates >> unneeded dependencies with the underlying BIOS/bootloader. For example, >> the driver unfortunately does not work as expected when booting from >> Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP >> does not set up some SPI controller settings to make the driver happy. >> Now such limitation has been removed with this series. > > Hi Bin > > Just starting to test these on Rangeley and got a question: We have two SPI flashes on CS0 resp. CS1 > and the mtd driver seems to only map the first of those flashes. Is this intentional or > are we missing something? > All the boards I have tested only have one SPI flash. Mika, any comments? Regards, Bin